C165H

Features:

C165H is a new low-cost member of the Infineon Communication Controller family. The device has the following features:
• C166 Static Core with Peripherals including:
  Full-static core up to 18 MIPS (@36 MHz)
  Peripheral Event Controller (PEC) for 8 independent DMA channels
  16 Dynamically Programmable Priority-Level Interrupt System
  Eight External Interrupts
  Up to 72 SW-configurative Input/Output (I/O) Ports, some with Interrupt Capabilities
  8-bit or 16-bit External Data Bus
  Multiplexed or Demultiplexed Address/Data Bus
  Up to 8-Mbyte Linear Address Space for Code and Data
  Five Programmable Chip-Select Lines with Wait-State Generator Logic
  On-Chip 3,072-Byte Dual-Port SRAM for user applications
  On-Chip 1,024-Byte Special Function Register Area
  On-Chip PLL with Output Clock Signal
  Five Multimode General Purpose Timers
  On-Chip Programmable Watchdog Timer
  Glueless Interface to EPROM, Flash EPROM and SRAM
  Low-Power Management Supporting Idle-, Power-Down- and Sleep-Mode and additional CPU clock slow-down mode with mode control for each peripheral
  USART interface with Auto Baud Rate detection up to 230.4 kbit/s
  USART Baud Rate generation in asynchronous mode up to 2.25 MBaud @ 36 MHz
  USART Baud Rate generation in synchronous mode up to 4.5 MBaud @ 36 MHz
  USART standard Baud Rates generation with very small deviation (230.4 kBaud < 0.01%, 460.8 kBaud < 0.15 %, 691.2 kBaud < 0.04 %, 921.6 kBaud < 0.15 % ) @ 36 MHz
  High speed Serial Synchronous Channel Interface (SSC) with ALIS-3.0 and AC97 compatibility up to 18 MBaud in SSC Master Mode and up to 9 MBaud in SSC Slave Mode @ 36 MHz
• ISDN Terminal Adapter Features including:
  Four Independent Full-Duplex HDLC Controllers
  IOM-2/PCM interface supporting TE, LT and PCM mode
  MON and CI1/CI2-Handler
  Two D-Channels
  Two B-Channels Supported
  Concatenated 2B+D channel Support
  Two Intercommunication Channels IC1, IC2
  D-Channel Access Control to first IOM channel-0 by S/G bit
  CDA Channel Access to individual IOM-2/PCM channels by SW
• On-Chip PLL for CPU clock generation
• External crystal and direct driven input clock frequency can vary between 4 and 20 MHz dependent on the CPU target clock frequency.
• Single and variable crystal clock input frequency
• Bootstrap Loader support via USART interface
• On-Chip Debug Support (OCDS)
• JTAG Boundary Scan Test support according to IEEE 1149.1
• 3.3 V single supply voltage
• 5 V (TTL-) tolerant I/Os
• C165H is available in 144-Pin P-TQFP package
• Operating temperature range: -40°C to + 85°C.


Pinout




Specifications

• Storage temperature (T_ST) -65 to +150 °C
• Voltage on V_DD pins with respect to ground (V_SS) -0.5 to + 4.0 V
• Voltage on any pin with respect to ground (V_SS) (except V_DD , V_SS, XTAL pins) -0.5 to 5.5 V
• Absolute maximum total I/O current 250 mA
• Absolute maximum current on any pin, sink or source 10 mA

Stresses beyond those listed above may cause permanent damage to the device. This is a stress rating only, and functional operation of the C165H is not implied at these or any other conditions above those indicated in the operational sections of this specification. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.


Description

C165H is a new low cost member of the Infineon Communication Controller family using low power CMOS technology. The device combines the successful Infineon C166 16-bit full-static core with four independent HDLC controllers, IOM-2 interface and 3-kbyte of Dual-Port on-chip RAM to a Intelligent Terminal Adapter with HDLC support.

C165H adresses all high feature ISDN TA, Intelligent NT or SOHO PBX designs, offering up to 18 MIPS along with legacy peripherals such as USART, SCI and Timers.