BU2092

Features: 1) Low power dissipation.2) Operating voltages ranging from 2.7 to 5.5V.3) Output is Nch open drain.4) High output withstand voltage of + 25V.5) Diverse variety of packages. BU2090 / F / FS: DIP16, SOP16, SSOP-A16 BU2092 / F / FV: DIP18, SOP18, SSOP-A18 (plastic molds)6) High drive capab...

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SeekIC No. : 004303167 Detail

BU2092: Features: 1) Low power dissipation.2) Operating voltages ranging from 2.7 to 5.5V.3) Output is Nch open drain.4) High output withstand voltage of + 25V.5) Diverse variety of packages. BU2090 / F / F...

floor Price/Ceiling Price

Part Number:
BU2092
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

1) Low power dissipation.
2) Operating voltages ranging from 2.7 to 5.5V.
3) Output is Nch open drain.
4) High output withstand voltage of + 25V.
5) Diverse variety of packages.
    BU2090 / F / FS: DIP16, SOP16, SSOP-A16
    BU2092 / F / FV: DIP18, SOP18, SSOP-A18
    (plastic molds)
6) High drive capability; direct lighting of green LED possible.



Application

Radio cassette players, telephones, compact audio systems, car stereos, and others


Specifications

Parameter Symbol Limits Unit
Power supply voltage VDD 0.3 ~ + 7.0 V
Power
dissipation
BU2090 / F / FS Pd 1000 (DIP), 300 (SOP), 500 (SSOP)1 mW
BU2092 / F / FV 1050 (DIP), 450 (SOP), 400 (SSOP)1
Power
dissipation
BU2090 / F / FS Pd 500 (SOP)2 , 650 (SSOP)3 mW
BU2092 / F / FV 500 (SOP)2 , 650 (SSOP)4
Operating temperature Topr 25 ~ + 75
Storage temperature Tstg 55 ~ + 125
Input voltage VIN VSS 0.3 ~ VDD + 0.3 V
Output voltage VO VSS ~ 25.0 V

1 Unmounted
2 When mounted on a glass epoxy board of 50mm  50mm  1.6mm
3 When mounted on a glass epoxy board of 90mm  50mm  1.6mm
4 When mounted on a glass epoxy board of 70mm  70mm  1.6mm




Description

The BU2090, BU2090F, BU2090FS, BU2092, BU2092F, and BU2092FV are 12-bit serial input, parallel output drivers.

For the BU2090 / F / FS, data input is shifted to the 12-bit internal shift register on the rising edge of a clock pulse. On the falling edge of the pulse, if the DATA pin is HIGH, the data in the shift register is output in parallel to Q0 to Q11.

For the BU2092 / F / FV, shift data read at the rising edge of CLOCK is output in parallel to Q0 to Q11 at the rising edge of LCK. These ICs also have an OE pin, which when HIGH, forces data to be output, regardless of the shift data state.


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