BCM8704

Description

The BCM8704 Ethernet/Fibre Channel LAN PHY is a fully integrated serialization/deserialization (10.3125-Gbps/10.5188-Gbps) interface device and the BCM8704 performs the extension functions for a 10-gigabit serial Ethernet reconciliation sublayer (RS) interface. The XGXS, PCS, and PMA functions include 8B/10B coding, 64B/66B coding, SerDes, clock multiplication unit (CMU), and clock and data recovery (CDR).

On-chip clock synthesis of BCM8704 is performed by the high-frequency low-jitter PLLs for the PMD and XAUI output retimers. Individual PMD and XAUI clock recovery is performed on the device by synchronizing the on-chip VCOs directly to their respective incoming data streams. Elastic buffers are provided to allow the XAUI and PMD interfaces to operate in asynchronous configuration. An external 156.25-MHz/159.38-MHz VCXO is required for clock cleanup mode.