B9946

Features: • 160-MHz Clock Support• LVCMOS/LVTTL Compatible Inputs• 10 Clock Outputs: Drive up to 20 Clock Lines• 1X or 1/2X Configurable Outputs• Output Three-state Control• 250 ps Maximum Output-to-Output Skew• Pin Compatible with MPC946• Industrial...

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B9946 Picture
SeekIC No. : 004295351 Detail

B9946: Features: • 160-MHz Clock Support• LVCMOS/LVTTL Compatible Inputs• 10 Clock Outputs: Drive up to 20 Clock Lines• 1X or 1/2X Configurable Outputs• Output Three-state Con...

floor Price/Ceiling Price

Part Number:
B9946
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• 160-MHz Clock Support
• LVCMOS/LVTTL Compatible Inputs
• 10 Clock Outputs: Drive up to 20 Clock Lines
• 1X or 1/2X Configurable Outputs
• Output Three-state Control
• 250 ps Maximum Output-to-Output Skew
• Pin Compatible with MPC946
• Industrial Temp. Range: 40°C to +85°C
• 32-Pin TQFP Package



Pinout

  Connection Diagram


Specifications

Maximum Input Voltage Relative to VSS: ...........  VSS 0.3V
Maximum Input Voltage Relative to VDD: ............VDD + 0.3V
Storage Temperature: ...............................65to + 150
Operating Temperature: ..............................40 to +85
Maximum ESD Protection.............................................. 2 KV
Maximum Power Supply: ...............................................5.5V
Maximum Input Current:...........................................±20 mA



Description

The B9946 is a low-voltage clock distribution buffer with the capability to select one of two LVCMOS/LVTTL compatible in-put clocks. These clock sources can be used to provide for test clocks as well as the primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 10 outputs are 3.3V LVCMOS or LVTTL compatible and can drive two series terminated 50Ω transmission lines. With this capability the B9946 has an effective fanout of 1:20.

The B9946 is capable of generating 1X and 1/2X signals from a 1X source. These signals are generated and retimed inter-nally to ensure minimal skew between the 1X and 1/2X sig-nals. SEL(A:C) inputs allow flexibility in selecting the ratio of 1X to1/2X outputs.

The B9946 outputs can also be three-stated via MR/OE# in-put. When MR/OE# is set HIGH, it resets the internal flip-flops and three-states the outputs.


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