Features: SpecificationsDescription The B5W Series has the following features including Low profile: 3.4 mm (Max.);Common mode impedance of 220 at 100 MHz (typical); Operating temperature: -10°C to +60°C;Storage temperature: -25°C to +70°C;Suitable for reflow soldering;Packaged on 2,000 piece ...
B5W Series: Features: SpecificationsDescription The B5W Series has the following features including Low profile: 3.4 mm (Max.);Common mode impedance of 220 at 100 MHz (typical); Operating temperature: -10°C...
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The B5W Series has the following features including Low profile: 3.4 mm (Max.);Common mode impedance of 220 at 100 MHz (typical); Operating temperature: -10°C to +60°C;Storage temperature: -25°C to +70°C;Suitable for reflow soldering;Packaged on 2,000 piece reels.
The B5W is a dual wound common mode chokeideal for common mode noise attenuation intwisted pair cable interfaces as well as IEEE 1394applications. An excellent impedance balancebetween two sets of twisted pairs is achieved bywinding across a single core. One B5W commonmode choke coil per interface port is possible withthis dual winding configuration.
Stresses in excess of the absolute Maximum Ratings can cause permanent damage to the device. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this document. Exposure to absoluteMaximum Rating for extended periods of the time can adversely affect reliability.Minimum and maximum values are testing requirements. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.In order to facilitate data busing, three-state outputs (Q0 to Q3) are provided on the data output lines, while the load condition of the register can be detected by the state of the DOR output. A HIGH on the three-state control flag (output enable input OE) forces the outputs into the high-impedance OFF-state mode. Note that the shift-out signal, unlike that in the CD40105B, is independent of the three-state output control. In the CD40105B, the three-state control must not be shifted from High to Low when the shift-out signal is Low (data loss would occur). In the high-speed CMOS version this restriction has been eliminated.
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