PinoutStorage Temperature . . . . . . . . . . . .. ...............................................65to +150
Ambient Temperature Under Bias. . . . . . . . ................................................ 0 to 70
Supply Voltage referenced to
AVSS or DVSS (AVDD, DVDD) . . . . . . . . . . . . ...........................................0.3 to +6V
Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect reliability. Programming conditions may differ.
DescriptionThe Am79C983A Integrated Multiport Repeater 2 (IMR2) chip is a VLSI integrated circuit that provides a system-level solution to designing intelligent (managed) multiport repeaters. When the IMR2 device is combined with the Quad Integrated Ethernet Transceiver (QuIET) device, it provides a cost-effective solution to designing 10BASE-T managed repeaters. The IMR2 device integrates the repeater functions specified by Section 9 (Repeater Unit) and Section19 (Layer Management for 10 Mb/s Baseband Repeaters) of the IEEE 802.3 standard.
The Am79C983A IMR2 device provides 1 standard Attachment Unit Interface (AUI) port, 12 Pseudo Attachment Unit Interface (PAUI) ports, and 1 Reversible AUI (RAUI) port for direct connection to a media access controller (MAC). The pseudo AUI ports can be connected to external transceivers to support multiple media types, including 10BASE2, 10BASE-T, and 10BASE-FL/FOIRL. The pseudo AUI ports can be turned off individually (without external circuitry) to allow the switching of transceiver ports between IMR2 devices. This capability allows multiple IMR2 devices to be connected to a single set of transceivers, thus allowing straightforward implementations of port switching applications.
The IMR2 Am79C983A also provides a Hardware Implemented Management Information Base (HIMIB™), which is a super set of the functions provided by the Am79C987 HIMIB device. All of the necessary counters, attributes, actions, and notifications specified by Section 19 of the IEEE 802.3 standard are included in the IMR2 device. To facilitate the design of managed repeaters, the IMR2 device implements a simple 8-bit microprocessor interface.
Support for an RMON MIB, as specified by the Internet Engineering Task Force (IETF) RFC 1757, is provided. Direct support is from an RMON Register Bank. Additional support is provided by the Packet Report Port, which supplies information that can be used in conjunction with a microprocessor to derive various RMON MIB attributes. With systems using multiple IMR2 de
Am79C983A Data Sheet
