Am79C975

The Am79C973 and Am79C975 controllers are singlechip 32-bit full- duplex, 10/100-Megabit per second (Mbps) fully integrated PCI-to-Wire Fast Ethernet system solution, designed to address high-performance system application requirements. They are flexible bus mastering device that can be used in any application, including network-ready PCs and bridge/router designs. The bus master architecture provides high data throughput and low CPU and system bus utilization. The Am79C973 and Am79C975 controllers are fabricated with advanced low-power 3.3-V CMOS process to provide low operating current for power sensitive applications.

The third generation Am79C973 and Am79C975 Fast Ethernet controllers also have several enhancements over their predecessors, the Am79C971 and Am79C972 devices. Besides integrating the complete 10/100 Physical Layer (PHY) interface, they further reduce system implementation cost by integrating the SRAM buffers on chip.

The Am79C973 and Am79C975 controllers contain 12- kilobyte (Kbyte) buffers, the largest of their class in 10/ 100 Mbps Ethernet controllers. The large internal buffers are fully programmable between the RX and TX queues for optimal performance.

The Am79C973 and Am79C975 controllers contain 12- kilobyte (Kbyte) buffers, the largest of their class in 10/ 100 Mbps Ethernet controllers. The large internal buffers
are fully programmable between the RX and TX queues for optimal performance.The Am79C973 and Am79C975 controllers are also compliant with PC98/PC99 and Wired for Management specifications. They fully support Microsoft's OnNow and ACPI specifications, which are backward compatible with Magic Packet technology and compliant with the PCI Bus Power Management Interface Specification by supporting the four power management states (D0, D1, D2, and D3), the optional PME pin, and the necessary configuration and data registers.

The Am79C973 and Am79C975 controllers are complete Ethernet nodes integrated into a single VLSI device. It contains a bus interface unit, a Direct Memory Access (DMA) Buffer Management Unit, an ISO/IEC 8802-3 (IEEE 802.3)- compliant Media Access Controller(MAC), a large Transmit FIFO and a large Receive FIFO, and an IEEE 802.3-compliant 10/100 Mbps PHY.

The integrated 10/100 PHY unit of the Am79C973 and Am79C975 controllers implement the complete physical layer for 10BASE-T and the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) functionality for 100BASE-TX, including MLT-3 encoding/decoding. It also supports 100BASE-FX operation by providing a Pseudo-ECL (PECL) interface for direct connection to a fiber optic transceiver module. The internal 10/100 PHY implements Auto-Negotiation for twisted-pair (10T/100TX) operation by using a modified 10BASE-T link integrity test pulse sequence as defined in the IEEE 802.3u specification. The Auto-Negotiation function automatically configures the controller to operate at the maximum performance level supported across the network link.

The Am79C975 controller also implements a Serial Management Interface in addition to the advanced management features offered with the Am79C973 controller. The Serial Management Interface is based on the industry standard Inter-IC (I2C) and System Management Bus (SMBus) specifications and enables a system to communicate with another network station for remote monitoring and alerting of local system management parameters and events. This simple yet powerful Serial Management Interface is capable of communicating within the system and over the network during normal operation or in low-power modes, even if the device is not initialized or set up for transmit or receive operation by the network software driver.

The 32-bit multiplexed bus interface unit provides a direct interface to the PCI local bus, simplifying the design of an Ethernet node in a PC system. The Am79C973 and Am79C975 controllers provide the complete interface to an Expansion ROM or Flash device allowing add-on card designs with only a single load per PCI bus interface pin. With their built-in support for both little and big endian byte alignment, thecontrollers also address non-PC applications. The Am79C973 and Am79C975 controllers' advanced CMOS design allows the bus interface to be connected to either a +5-V or a +3.3-V signaling environment. A compliant IEEE 1149.1 JTAG test interface for boardlevel testing is also provided, as well as a NAND tree test structure for those systems that cannot support the JTAG interface.

The Am79C973 and Am79C975 controllers support auto-configuration in the PCI configuration space. Additional Am79C973 and Am79C975 controller configuration parameters, including the unique IEEE physical address, can be read from an external non-volatile memory (EEPROM) immediately following system reset.

In addition, the Am79C973 and Am79C975 controllers provide programmable on-chip LED drivers for transmit, receive, collision, link integrity, Magic Packet status, activity, link active, address match, full-duplex, 10 Mbps or 100 Mbps, or jabber status.

The Am79C973 and Am79C975 controllers are register compatible with the LANCE™ (Am7990) Ethernet controller, the C-LANCE™ (Am79C90) Ethernet controller, and all Ethernet controllers in the PCnet™ Family, except ILACC™ (Am79C900), including the PCnet- ISA™ (Am79C960), PCnet-ISA+™ (Am79C961), PCnet- ISA II™ (Am79C961A), PCnet -32™ (Am79C965), PCnet -PCI™ (Am79C970), PCnet-PCI II™ (Am79C970A), PCnet-FAST™ (Am79C971), and PCnet-FAST+™ (Am79C972). The Buffer Management Unit supports the LANCE and PCnet descriptor software models.

The Am79C973 and Am79C975 controllers are ideally suited for LAN on the motherboard, network adapter card, and embedded designs. It is available in a 160- pin Plastic Quad Flat Pack (PQFP) package and also in a 176-pin Thin Quad Flat Pack (TQFP) package for form factor sensitive designs.