Am79C971

The Am79C971 controller is a single-chip 32-bit full-duplex, 10/100-Megabit per second (Mbps) highlyintegrated Ethernet system solution, designed to address high-performance system application requirements. It is a flexible bus mastering device that can be used in any application, including network-ready PCs and bridge/router designs. The bus master architecture provides high data throughput in the system and low CPU and system bus utilization. The Am79C971 controller is fabricated with AMD's advanced low-power Complementary Metal Oxide Semiconductor (CMOS) process to provide low operating and standby current for power sensitive applications.

The Am79C971 controller is a complete Ethernet node integrated into a single VLSI device. It contains a bus interface unit, a Direct Memory Access (DMA) Buffer Management Unit, an ISO/IEC 8802-3 (IEEE 802.3)- compliant Media Access Controller (MAC), a large Transmit FIFO and a large Receive FIFO, SRAMbased FIFO extension with support for up to 128K bytes of external frame buffering, an IEEE 802.3u-compliant MII, an IEEE 802.3-compliant Twisted-Pair Transceiver Media Attachment Unit (10BASE-T MAU), and an IEEE 802.3-compliant Attachment Unit Interface (AUI). Both proprietary full-duplex and IEEE 802.3 compliant half-duplex operation are supported on the MII, AUI, GPSI, and 10BASE-T MAU interfaces. 10- Mbps operation is supported through the MII, AUI, and 10BASE-T MAU interfaces, and 100 Mbps operation is supported through the MII. The 10BASE-T MAU interface includes an IEEE 802.3-compliant auto-negotiation implementation, which will automatically negotiate between half- and full-duplex with another IEEE 802.3- compliant auto-negotiation 10BASE-T device.

The Am79C971 controller is register compatible with the LANCE  (Am79C90) Ethernet controller, and all Ethernet controllers in the PCnet Family except ILACC (Am79C900), including the PCnet-ISA controller (Am79C960),PCnet-ISA+ controller (Am79C961), PCnet-ISA II controller (Am79C961A), PCnet-32 cont rol l e r (Am79C965), PCnet -PCI con t rol ler (Am79C970), and PCnet -PCI I I con t rol ler (Am79C970A). The Buffer Management Unit supports the LANCE and PCnet descriptor software models.
The 32-bit multiplexed bus interface unit provides a direct interface to the PCI local bus, simplifying the design of an Ethernet node in a PC system. The Am79C971 controller provides the complete interface to an Expansion ROM or Flash device allowing add-on card designs with only a single load per PCI bus interface pin. With its built-in support for both little and big endian byte alignment, this controller also addresses non-PC applications. The Am79C971 controller's advanced CMOS design allows the bus interface to be connected to either a +5-V or a +3.3-V signaling environment. A compliant IEEE 1149.1 JTAG test interface for board-level testing is also provided, as well as a NAND tree test structure for those systems that cannot support the JTAG interface.

The Am79C971 controller supports auto-configuration in the PCI configuration space. Additional Am79C971 controller configuration parameters, including the unique IEEE physical address, can be read from an external non-volatile memory (EEPROM) immediately following system reset.

The integrated Manchester encoder/decoder (MENDEC) eliminates the need for an external Serial Interface Adapter (SIA) in the system. The built-in GPSI allows the MENDEC to be bypassed.
In addition, the device provides programmable on-chip LED drivers for transmit, receive, collision, receive polarity, link integrity, activity, link active, address match,
full-duplex, MII select, 100 Mbps, or jabber status. The Am79C971 controller also provides an EADI to allow external hardware address filtering in internetworking applications and a receive frame tagging feature.

For power sensitive applications where low standby current is desired, the device incorporates two sleep functions to reduce overall system power consumption, excellent for notebooks and green PCs. In conjunction with these low power modes, the PCnet-FAST controller also has integrated functions to support Magic Packet technology, an inexpensive technology that allows remote wake up of networked PCs.

The controller has the capability to automatically select either the MII, AUI, or Twisted-Pair transceiver. Only one interface is active at any one time. Any of the network
interfaces can be programmed to operate in either half-duplex or full-duplex mode (AUI full-duplex only supports the 10BASE-F standard).

The dual Transmit and Receive FIFOs optimize system overhead, providing sufficient latency tolerance at 10 Mbps and for 100-Mbps systems where low latenciescan be guaranteed during frame transmission and reception.

In highly loaded 10-Mbps systems, such as servers or when using the controller in a 100-Mbps environment, the additional frame buffering capability provided by a
16-bit wide SRAM interface provides high performance and high latency tolerance on the system bus and network.

The Am79C971 controller can use up to 128 Kbytes of SRAM as an extension of its dual Transmit and Receive FIFOs. When no SRAM is used, the Am79C971 controller's
FIFOs are programmed to bypass the SRAM interface.

IMPORTANT NOTE: A "No SRAM configuration" is only valid for 10Mb mode. In 100Mb mode, SRAM is mandatory and must always be used.

ISO/IEC 8802-3 and IEEE 802.3 will be used interchangeably when referring to half-duplex 10 Mbps networks. IEEE 802.3 or IEEE 802.3u will be used interchangeably only when referring to half-duplex 100- Mbps Ethernet networks, since the IEEE standard is not ISO approved yet. Full-duplex is a proprietary standard and is not approved by IEEE or ISO.