Am29PDL129H

Features: `Ready/Busy# pin (RY/BY#)- Provides a hardware method of detecting program or erase cycle completion`Hardware reset pin (RESET#)- Hardware method to reset the device to reading array data`WP#/ACC (Write Protect/Acceleration) input- At VIL, hardware level protection for the first and last...

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SeekIC No. : 004282383 Detail

Am29PDL129H: Features: `Ready/Busy# pin (RY/BY#)- Provides a hardware method of detecting program or erase cycle completion`Hardware reset pin (RESET#)- Hardware method to reset the device to reading array data`...

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Part Number:
Am29PDL129H
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Features:

`Ready/Busy# pin (RY/BY#)
- Provides a hardware method of detecting program or erase cycle completion
`Hardware reset pin (RESET#)
- Hardware method to reset the device to reading array data
`WP#/ACC (Write Protect/Acceleration) input
- At VIL, hardware level protection for the first and last two 4K word sectors.
- At VIH, allows removal of sector protection
- At VHH, provides accelerated programming in a factory setting
`Persistent Sector Protection
- A command sector protection method to lock combinations of individual sectors and sector groups to prevent  rogram or erase operations within that sector
- Sectors can be locked and unlocked in-system at VCC level
`Password Sector Protection
- A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password
`Package options
- 80-ball Fine-pitch BGA
- Multi Chip Packages (MCP)




Specifications

Plastic Packages . . . . . . . . . . . . 65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . .. . 65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . .0.5 V to +4.0 V
A9, OE#, and RESET#
(Note 2). . . . . . . . . . . . . . . . . . . .0.5 V to +13.0 V
(Note 2) . . . . . . . . . . . . . . . . . . .0.5 V to +10.5 V
All other pins (Note 1) . . . . . . 0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See . During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 7.

2. Minimum DC input voltage on pins A9, OE#, RESET#,  and WP#/ACC is 0.5 V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot VSS to 2.0 V for periods of up to 20 ns. See . Maximum DC input voltage on pin A9, OE#, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.




Description

The Am29PDL129H is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 Mwords. The device is offered in an 80-ball Finepitch BGA package, and various multi-chip packages. The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations.

Am29PDL129H offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to 85 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE1#, CE2#), write enable (WE#) and output enable (OE#) controls. Dual Chip Enables allow access to two 64 Mbit partitions of the 128 Mbit memory space.




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