Am29LV642D

Pinout




Specifications

Storage Temperature
Plastic Packages . . . . . . . . . . . . . ..  . 65 to +150
Ambient Temperature
with Power Applied . . . . . . . . . .  .. . . 65 to +125
Voltage with Respect to Ground
V_CC (Note 1) . . . . . . . . . . . . . . . . . . .0.5 V to +4.0 V
V_IO . . . . . . . . . . . . . . . . . . . .  .. . . . ..0.5 V to +5.5 V
A9, OE#, ACC, and RESET#
(Note 2) . . . . . . . . . . . . . . . . . . . . . .0.5 V to +12.5 V
All other pins (Note 1) . . . . .  .. .0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA


Description

The Am29LV642D is a 128 Mbit, 3.0 Volt (3.0 V to 3.6 V) single power supply flash memory device organized as two Am29LV640D dice in a single 64-ball Fortified BGA package. Each Am29LV640D is a 64 Mbit, 3.0 Volt (3.0 V to 3.6 V) single power supply flash memory device organized as 4,194,304 words. Data appears on DQ0-DQ15. The device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The Am29LV642D is equipped with two CE# pins for flexible selection between the two internal 64 Mb devices. The device can also be programmed in standard EPROM programmers.
The Am29LV642D offers access times of 90 and 120 ns and is offered in a 64-ball Fortified BGA package. To eliminate bus contention the Am29LV642D device has two separate chip enables (CE# and CE2#). Each chip enable (CE# or CE2#) is connected to only one of the two dice in the Am29LV642D package. To the system, this device will be the same as two independent Am29LV640D on the same board. The only difference is that they are now packaged together to reduce board space.

Each Am29LV642D requires only a single 3.0 Volt power supply (3.0 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard.

Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm-an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm-an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, Am29LV642D automatically times the erase pulse widths and verifies proper cell margin.

The VersatileI/O™ (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin. This allows Am29LV642D to operate in 1.8 V, 3 V, or 5 V system environment as required. For voltage levels below 3 V, contact an AMD representative for more information.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, by reading the DQ7 (Data# Polling), or DQ6 (toggle) status bits. After a program or erase cycle has been completed, Am29LV642D is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device.

Am29LV642D offers a standby mode as a power-saving feature. Once the system places the device into the standby mode power consumption is greatly reduced. The accelerated program (ACC) feature allows the system to program the device at a much faster rate. When ACC is pulled high to VHH, the device enters the Unlock Bypass mode, enabling the user to reduce the time needed to do the program operation. This feature is intended to increase factory throughput during system production, but may also be used in the field if desired.

AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. Am29LV642D electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.