Am29LL800B

PinoutDescriptionThe Am29LL800B is an 8 Mbit, 2.2 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 44-pin SO and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15DQ0; the byte-wide (x8) data appears on DQ7 DQ0. This device requires only a ...

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SeekIC No. : 004282316 Detail

Am29LL800B: PinoutDescriptionThe Am29LL800B is an 8 Mbit, 2.2 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 44-pin SO and 48-pin TSOP packages. The word-wide dat...

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Part Number:
Am29LL800B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/8/14

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Description

The Am29LL800B is an 8 Mbit, 2.2 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 44-pin SO and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15DQ0; the byte-wide (x8) data appears on DQ7 DQ0. This device requires only a single, 2.2 volt VCC supply to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device.

This device is manufactured using AMD's 0.35 m process technology, and offers all the features and benefits of the Am29LV800, which was manufactured using 0.5 m process technology. In add i tion, the Am29LL800B features unlock bypass programming and in-system sector protection/unprotection.

The standard device offers access times of 150 and 200 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 2.2 volt power supply for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations.

Am29LL800B is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm-an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.




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