Am29DL400BB-70EC

Features:

The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm-an internal algorithm that auto matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.


Pinout




Specifications

Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . 65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . .. 65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . .  . . . . .0.5 V to +4.0 V
A9, OE#and RESET# (Note 2) . . . . .. .0.5 V to +12.5 V
All other pins (Note 1) . . . . . .  . ..  0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3)  . . . .  . . .  200 mA


Description

The Am29DL400BB-70EC is an 4 Mbit, 3.0 volt-only flash memory device, organized as 262,144 words or 524,288 bytes. The device is offered in 44-pin SO and 48-pin TSOP packages. The word-wide (x16) data appears on DQ0DQ15; the byte-wide (x8) data appears on DQ0DQ7. This device requires only a single 3.0 volt VCC supply to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device.

The standard Am29DL400BB-70EC device offers access times of 70, 80, 90, and 120 ns, allowing high-speed microprocessors to operate without wait states. Standard control pinschip enable (CE#), write enable (WE#), and output enable (OE#)-control read and write operations, and avoid bus contention issues.