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Am29BL802C

Features: The Am29BL802C offers a Linear Burst mode-a32 word sequential burst with wrap around-in abottom boot configuration only. This devices requireadditional control pins for burst operations: LoadBurst Address (LBA#), Burst Address Advance(BAA#), and Clock (CLK). This implementation allowseas...

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SeekIC No. : 004282206 Detail

Am29BL802C: Features: The Am29BL802C offers a Linear Burst mode-a32 word sequential burst with wrap around-in abottom boot configuration only. This devices requireadditional control pins for burst operations: L...

Am29BL802C Data Sheet

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Part Number:
Am29BL802C
Supply Ability:
5000

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  • 1~5000
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  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

The Am29BL802C offers a Linear Burst mode-a32 word sequential burst with wrap around-in abottom boot configuration only. This devices requireadditional control pins for burst operations: LoadBurst Address (LBA#), Burst Address Advance(BAA#), and Clock (CLK). This implementation allowseasy interface with minimal glue logic to a wide rangeof microprocessors/microcontrollers for high perfor-mance read operations.




Pinout

Connection Diagram


Specifications

Storage Temperature
Plastic Packages . . . . . . . . . . . . . 65°C to +150°C
Ambient Temperature
with Power Applied  . . . . . . . . . . 65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . .0.5 V to +4.0 V
A9, OE#, and RESET# (Note 2) . ...0.5 V to +13.0 V
All other pins (Note 1). . . . . . . . . . .0.5 V to +5.5 V
Output Short Circuit Current (Note 3)  . . . . . 200 mA


Description

The Am29BL802C is an 8 Mbit, 3.0 Volt-only burstmode Flash memory devices organized as 524, 288words. The device is offered in a 56-pin SSOPpackage. These devices are designed to be pro-grammed in-system with the standard system 3.0-voltVCC supply. A 12.0-volt VPP or 5.0 VCC is not requiredfor program or erase operations. The device can alsobe programmed in standard EPROM programmers.

Am29BL802C offers access times of 65, 70, 90, and 120ns, allowing high speed microprocessors to operatewithout wait states. To eliminate bus contention thedevice has separate chip enable (CE#), write enable(WE#) and output enable (OE#) controls.




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