Am29BDS640G

Features: Sector Protection - Software command sector locking Reduced Wait-State Handshaking feature available- Provides host system with minimum possible latency by monitoring RDY Hardware reset input (RESET#)- Hardware method to reset the device for reading array data WP# input- Write protect (...

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SeekIC No. : 004282201 Detail

Am29BDS640G: Features: Sector Protection - Software command sector locking Reduced Wait-State Handshaking feature available- Provides host system with minimum possible latency by monitoring RDY Hardware reset i...

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Part Number:
Am29BDS640G
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/6/6

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Product Details

Description



Features:

Sector Protection
- Software command sector locking
Reduced Wait-State Handshaking feature available
- Provides host system with minimum possible latency by monitoring RDY
Hardware reset input (RESET#)
- Hardware method to reset the device for reading array data
WP# input
- Write protect (WP#) function protects sectors 0 and 1 (bottom boot), or sectors 132 and 133 (top boot), regardless of sector protect status
ACC input: Acceleration function reduces programming time; all sectors locked when ACC = VIL
CMOS compatible inputs, CMOS compatible outputs
Low VCC write inhibit
Supports Common Flash Memory Interface (CFI)
Software command set compatible with JEDEC 42 standards
- Backwards compatible with Am29F and Am29LV families
Data# Polling and toggle bits
- Provides a software method of detecting program and erase operation completion
Erase Suspend/Resume
- Suspends an erase operation to read data from, or program data to, a sector that is not being erased,then resumes the erase operation
Unlock Bypass Program command
- Reduces overall programming time when issuing multiple program command sequences




Specifications

Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . 65°C to +150°C
Ambient Temperature
with Power Applied  . . . . . . . . . . . . . 65°C to +125°C
Voltage with Respect to Ground:
All Inputs and I/Os except
as noted below (Note 1). . . . . . . 0.5 VIO to V  + 0.5 V
V  (Note 1). . . . . . . . . . . . . . . . . .0.5 VCC to +2.5 V
V  . . . . . . . . . . . . . . . . . . . . . . . . .0.5 VIO to +3.5 V
ACC . . . . . . . . . . . . . . . . . . . . . . .0.5 V to +12.5 V
Output Short Circuit Current (Note 3)  . . . . . . 100 mA



Description

The Am29BDS640G is a 64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, orga-
nized as 4,194,304 words of 16 bits each. This device uses a single V  of 1.65 to 1.95 V to read, program, and erase
the memory array. The device supports Enhanced VIO to offer up to 3V compatible inputs and outputs. A 12.0-volt VID may be used for faster program performance if desired. The device can also be programmed in standard EPROM programmers.
At 54 MHz, Am29BDS640G provides a burst access of 13.5 ns at 30 pF with a latency of 87.5 ns at 30 pF. At 40 MHz, the device provides a burst access of 20 ns at 30 pF with a latency of 95 ns at 30 pF. The device operates within the industrial temperature range of -40°C to +85°C. The device is offered in the 80-ball FBGA package.
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four
banks. Am29BDS640G can improve overall system performance by allowing a host system to program or erase in one bank,then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations.
The device is divided as shown in the following table:
  Connection Diagram
The Enhanced VersatileIO(TM) (VIO ) control allows the host system to set the voltage levels that Am29BDS640G enerates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin.This allows the device to operate in 1.8 V and 3 V system environments as required.
Am29BDS640G uses Chip Enable (CE#), Write Enable (WE#),Address Valid (AVD#) and Output Enable (OE#) to control
asynchronous read and write operations. For burst operations, the device additionally requires Ready (RDY), and
Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and wrap through the same memory space, or read the flash array in continuous mode.




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