ATUSBFUNC-SS7211

The Application Interface provides a simple mechanism to interface to the user logic. This interface allows direct access to all the endpoint FIFOs except for the control endpoint EP0. This block generates the signals for all other endpoint transfers and provides access to their respective FIFOs. For example, a bulk in transfer can be done to EP2 and setting, clearing of stall conditions are controlled by the application. EP1, EP2 and EP3 endpoints are controlled independently. This allows simultaneous access to these endpoints.

The ATUSBFUNC-SS7211 is a fully synthesizable core that can be implemented in any Atmel ASIC library (gate array or standard cell). The core is supported by a comprehensive USB test environment (ATUSBTEST-SS7400) that can be used to verify the entire design, including the application. The USB Function Core can be used in any high-speed (12 Mbps) application, such as a printer, camera or scanner. The core is configured before synthesis to respond to all standard USB hub/host commands. Up to four endpoints are supported. The ATUSBFUNC-SS7211 interface to the application consists of an application interface and a FIFO interface. There are no user programmable registers in this core. The internal state machine and control logic decode the hub/host commands and control the data transfers across the FIFO interface. Control signals are used to transfer error and status information to or from the application.