ATF1508ASVL

Features:

• High-density, High-performance, Electrically-erasable Complex Programmable Logic Device
3.0V to 3.6V Operating Range
128 Macrocells
5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
84, 100, 160 Pins
15 ns Maximum Pin-to-pin Delay
Registered Operation up to 77 MHz
Enhanced Routing Resources
• Flexible Logic Macrocell
D/T/Latch Configurable Flip-flops
Global and Individual Register Control Signals
Global and Individual Output Enable
Programmable Output Slew Rate
Programmable Output Open Collector Option
Maximum Logic Utilization by Burying a Register within a COM Output
• Advanced Power Management Features
Automatic 5 µA Standby for "L" Version
Pin-controlled 100 µA Standby Mode
Programmable Pin-keeper Inputs and I/Os
Reduced-power Feature per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 84-lead PLCC and 100-lead PQFP and TQFP and 160-lead PQFP Packages
• Advanced EE Technology
100% Tested
Completely Reprogrammable
10,000 Program/Erase Cycles
20 Year Data Retention
2000V ESD Protection
200 mA Latch-up Immunity
• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
• Fast In-System Programmability (ISP) via JTAG
• PCI-compliant
• Security Fuse Feature


Pinout




Specifications

Temperature Under Bias............................................................................................ -40°C to +85°C
Storage Temperature............................................................................................... -65°C to +150°C
Voltage on Any Pin with Respect to Ground ...............................................................-2.0V to +7.0V(1)
Voltage on Input Pins with Respect to Ground During Programming.........................-2.0V to +14.0V(1)
Programming Voltage with Respect to Ground .........................................................-2.0V to +14.0V(1)


Description

The ATF1508ASVL is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel's proven electrically-erasable technology. With 128 logic macrocells and up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs.The ATF1508ASV(L)'s enhanced routing switch matrices increase usable gate count and increase odds of successful pin-locked design modifications.
The ATF1508ASVL has up to 96 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individua-lly within each macrocell.
Each of the 128 macrocells generates a buried feedback that goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch ma-trix in each logic block then selects 40 individual signals from the global bus.Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1508ASVL allows fast, efficient generation of complex logic functions. The ATF1508ASV(L) contains eight such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms.
The ATF1508ASVL macrocell, shown in Figure 1, is flexible enough to support highly-complex logic functions operating at high-speed. The macrocell con-sists of five sections: product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and enable, and logic array in-puts.Unused macrocells are auto-matically disabled by the compiler to decrease power consumption. A security fuse,when programmed, protects the con-tents of the ATF1508ASVL. Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revi-sion or date. The User Signature is accessible regardless of the state of the security fuse.
The ATF1508ASVL device is an in-system programmable (ISP) device. It uses the industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully-compliant with JTAG's Boundary-scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.