ATF1508ASL

• High-density, High-performance, Electrically-erasable ComplexProgrammable Logic Device 128 Macrocells 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell 84, 100, 160 Pins 7.5 ns Maximum Pin-to-pin Delay Registered Operation up to 125 MHz Enhanced Routing Resources
• Flexible Logic Macrocell D/T/Latch Configured Flip-flops Global and Individual Register Control Signals Global and Individual Output Enable Programmable Output Slew Rate Programmable Output Open Collector Option Maximum Logic Utilization by Burying a Register within a COM Output
• Advanced Power Management Features Automatic 10 µA Standby for "L" Version Pin-controlled 1 mA Standby Mode Programmable Pin-keeper Inputs and I/Os Reduced-power Feature per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 84-lead PLCC, 100-lead PQFP, 100-lead TQFP and 160-lead PQFP Packages
• Advanced EE Technology 100% Tested Completely Reprogrammable 10,000 Program/Erase Cycles 20-year Data Retention 2000V ESD Protection 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
• Fast In-System Programmability (ISP) via JTAG
• PCI-compliant
• 3.3 or 5.0V I/O Pins
•Security Fuse Feature

The ATF1508ASL is a high-performance, high-density complex programmable logic device(CPLD) that utilizes Atmel's proven electrically-erasable technology. With 128 logic macrocellsand up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classicPLDs. The ATF1508AS's enhanced routing switch matrices increase usable gate count andincrease odds of successful pin-locked design modifications.

The ATF1508ASL has up to 96 bi-directional I/O pins and four dedicated input pins, dependingon the type of device package selected. Each dedicated pin can also serve as a global controlsignal, register clock, register reset or output enable. Each of these control signals can beselected for use individually within each macrocell.Each of the 128 macrocells generates a buried feedback that goes to the global bus. Eachinput and I/O pin also feeds into the global bus. The switch matrix in each logic block thenselects 40 individual signals from the global bus. Each macrocell also generates a foldbacklogic term that goes to a regional bus.

Cascade logic between macrocells in the ATF1508ASallows fast, efficient generation of complex logic functions. The ATF1508AS contains eightsuchlogicchains,eachcapableofcreatingsumtermlogicwithafan-inofupto40productterms.The ATF1508AS macrocell, shown in Figure 1, is flexible enough to support highly-complexlogic functions operating at high speed. The macrocell consists of five sections: product termsand product term select multiplexer; OR/XOR/CASCADE logic, a flip-flop, output select andenable, and logic array inputs.

Unused macrocells are automatically disabled by the compiler to decrease power consump-tion. A security fuse, when programmed, protects the contents of the ATF1508ASL. Two bytes(16 bits) of User Signature are accessible to the user for purposes such as storing projectname, part number, revision or date.

The User Signature is accessible regardless of the stateof the security fuse.The ATF1508ASL device is an in-system programmable (ISP) device. It uses the industry-stan-dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fullycompliant with JTAG's Boundary-scan Description Language (BSDL). ISP allows the device to be programmed without remov-ing it from the printedcircuit board. In addition to simplifying the manufacturing flow, ISP alsoallows design modifications to be made in the field via software.