AT60142E

Features:

• Operating Voltage: 3.3V
• Access Time:
      15 ns (Preview) for 3.3V biased only (AT60142E)
      17 ns and 20 ns for 5V Tolerant (AT60142ET)
• Very Low Power Consumption
      Active: 810 mW (Max) @ 15 ns
      Standby: 215 µW (Typ)
• Wide Temperature Range: -55 to +125°C
• 500 Mils Width Package
• TTL-Compatible Inputs and Outputs
• Asynchronous
• Designed on 0.25 Micron Process
• No Single Event Latch Up below LET Threshold of 80 MeV/mg/cm²
• Tested up to a Total Dose of 300 krads (Si) according to MIL-STD-883 Method 1019
• 500 Mils Wide FP36 Package
• ESD Better than 4000V



Pinout




Specifications

Supply Voltage to GND Potential: .......................... -0.5V + 4.6V DC Input Voltage:........................................GND -0.5V to 4.6V(1) DC Output Voltage High Z State: ....................GND -0.5V to 4.6V Storage Temperature: .................................. -65°C to + 150°C Output Current Into Outputs (Low): ................................. 20 mA Electro Statics Discharge Voltage:.......... > 4001V (MIL STD 883D Method 3015.3)

Description

The AT60142E/ET are very low power CMOS static RAM organized as 524 288 x 8 bits.Atmel brings the solution to applications where fast computing is as mandatory as lowconsumption, such as aeros-pace electronics, portable instruments, or embarked systems.

Utilizing an array of six transistors (6T) memory cells, the AT60142E/ET combine an extremely low standby supply current (Typical value = 65 µA) with a fast access time at 15 ns over the full military temperature range. The high stability of the 6T cell provides excellent protection against soft errors due to noise.

The E version is biased at 3.3 V and is not 5V tolerant: it is available to 15⁽¹⁾ and 20 ns specification.The ET(1) version is a variant allowing for 5V tolerance: it is available in 17 ns and 20ns specification.The AT60142E/ET are processed according to the methods of the latest revision of the MIL PRF 38535 or ESA SCC 9000.

AT60142E is produced on a radiation hardened 0.25 µm CMOS process.