Features: • Serial Peripheral Interface (SPI) Compatible• Supports SPI Modes 0 (0,0) and 3 (1,1)• 20 MHz Clock Rate• Byte Mode and 256-byte Page Mode for Program Operations• Sector Architecture: Two Sectors with 32K Bytes Each (512K) Four Sectors with 32K Bytes Each (...
AT25F512: Features: • Serial Peripheral Interface (SPI) Compatible• Supports SPI Modes 0 (0,0) and 3 (1,1)• 20 MHz Clock Rate• Byte Mode and 256-byte Page Mode for Program Operations...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Operating Temperature...................... -40°C to +85°C
Storage Temperature ...................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground ..........................-1.0V to +7.0V
Maximum Operating Voltage ............................... 6.25V
DC Output Current............................................. 5.0 mA
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
The AT25F512/1024 provides 524,288/1,048,576 bits of serial reprogrammable Flash memory organized as 65,536/131,072 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25F512/1024 is available in a space-saving 8-lead JEDEC SOIC package.
The AT25F512/1024 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are completely self-timed.
BLOCK WRITE protection for top 1/4, top 1/2 or the entire memory array (1M) or entire memory array (512K) is enabled by programming the status register. Separate write enable and write disable instructions of AT25F512 are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.