Features: • Serial Peripheral Interface (SPI) Compatible• Supports SPI Modes 0 (0,0) and 3 (1,1)• Low Voltage and Standard Voltage Operation 5.0 (VCC = 4.5V to 5.5V) 2.7 (VCC = 2.7V to 5.5V) 1.8 (VCC = 1.8V to 3.6V)• 3 MHz Clock Rate• 64-Byte Page Mode and Byte Wri...
AT25128: Features: • Serial Peripheral Interface (SPI) Compatible• Supports SPI Modes 0 (0,0) and 3 (1,1)• Low Voltage and Standard Voltage Operation 5.0 (VCC = 4.5V to 5.5V) 2.7 (VCC = 2...
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Operating Temperature ................................-55°C to +125°C
Storage Temperature ...................................-65°C to +150°C
Voltage on Any Pin
with Respect to Ground ....................................-1.0V to +7.0V
Maximum Operating Voltage........................................... 6.25V
DC Output Current ....................................................... 5.0 mA
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
The AT25128/256 provides 131,072/262,144 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The devices are available in space saving 8-pin PDIP (AT25128/256), 8-pin EIAJ SOIC (AT25128/256), 8-pin and 16-pin JEDEC SOIC (AT25128),14-pin TSSOP (AT25128), 20-pin TSSOP (AT25128/256),and 8-pin Leadless Array (AT25128/256) packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.
The AT25128/256 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely selftimed, and no separate ERASE cycle is required before WRITE.
BLOCK WRITE protection of AT25128 is enabled by programming the status register with top ¼, top ½ or entire array of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection of AT25128 is provided via the WP pin to protect against inadvertent write attempts to the status register The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.