AT-41485

Features: • Low Noise Figure: 1.4 dB Typical at 1.0 GHz 1.7 dB Typical at 2.0 GHz• High Associated Gain: 18.5 dB Typical at 1.0 GHz 13.5 dB Typical at 2.0 GHz• High Gain-Bandwidth Product: 8.0 GHz Typical fTSpecifications Symbol Parameter Units Absolute Maximum[1]...

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AT-41485 Picture
SeekIC No. : 004290073 Detail

AT-41485: Features: • Low Noise Figure: 1.4 dB Typical at 1.0 GHz 1.7 dB Typical at 2.0 GHz• High Associated Gain: 18.5 dB Typical at 1.0 GHz 13.5 dB Typical at 2.0 GHz• High Gain-Bandwidth ...

floor Price/Ceiling Price

Part Number:
AT-41485
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/12

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Product Details

Description



Features:

• Low Noise Figure:
  1.4 dB Typical at 1.0 GHz
  1.7 dB Typical at 2.0 GHz
• High Associated Gain:
  18.5 dB Typical at 1.0 GHz
  13.5 dB Typical at 2.0 GHz
• High Gain-Bandwidth
  Product: 8.0 GHz Typical fT



Specifications

Symbol
Parameter
Units
Absolute Maximum[1]
VEBO
Emitter-Base Voltage
V
1.5
VCBO
Collector-Base Voltage
V
20
VCEO
Collector-Emitter Voltage
V
12
IC
Collector Current
mA
60
PT
Power Dissipation [2,3]
mW
500
Tj
Junction Temperature
°C
150
TSTG
Storage Temperature
°C
-65 to 150



Description

  Hewlett-Packard's AT-41485 is a general purpose NPN bipolar transistor that offers excellent high frequency performance. The AT-41485 is housed in a low cost.085" diameter plastic package. The 4 micron emitter-to-emitter
pitch enables this transistor AT-41485 to be used in many different functions. The 14 emitter finger interdigitated geometry yields an intermediate sized transistor with impedances that are easy to match for low noise and moderate power
applications. Applications include use in wireless systems as an LNA, gain stage, buffer, oscillator, and mixer. An optimum noise match near 50 W at 900 MHz, makes AT-41485 easy to use as a low noise amplifier.

    The AT-41485 bipolar transistor is fabricated using Hewlett-Packard's 10 GHz fT Self-Aligned-Transistor (SAT) process. The die is nitride passivated for surface protection. Excellent device uniformity, performance and reliability are produced by the use of ionimplantation, self-alignment techniques, and gold metalization in the fabrication of AT-41485.


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