ASMP5P2309A

Features: SpecificationsDescriptionThe ASMP5P2309A has the following features including 10 MHz to 133-MHz operating range, compatible with CPU and PCI bus frequencies;Zero inputoutput propagation delay;Less than 200 ps cycle-to-cycle fitter is compatible with Pentium0 based systems;Test Mode to by...

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SeekIC No. : 004289110 Detail

ASMP5P2309A: Features: SpecificationsDescriptionThe ASMP5P2309A has the following features including 10 MHz to 133-MHz operating range, compatible with CPU and PCI bus frequencies;Zero inputoutput propagation de...

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Part Number:
ASMP5P2309A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:






Specifications






Description

The ASMP5P2309A has the following features including 10 MHz to 133-MHz operating range, compatible with CPU and PCI bus frequencies;Zero inputoutput propagation delay;Less than 200 ps cycle-to-cycle fitter is compatible with Pentium0 based systems;Test Mode to bypass PLL (ASM5P2309A only,refer Select Input Decoding Table).

ASM5P2309A  is  a  versatile,  3.3V  zero-delay  buffer designed to distribute high-speed clocks. ASMP5P2309A accepts one reference input and drives out nine low-skew clocks. It is available in a 16-pin package.It accepts  one reference input and drives out five low-skew clocks.The-1 H version of the ASM5P23XXA operates at up to 133- MHz frequencies, and has higher drive than the-1 devices. All parts of ASMP5P2309A have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.The ASM5P2309A has two banks of four outputs each,which can be controlled by the Select inputs as shown in the Select Input Decoding Table. If all the output clocks are not required, Bank B can be three-stated. The select input also allows  the input clock to be directly applied to the outputs for chip and system testing purposes.Multiple  ASM5P2309A  devices  can accept the same input clock and distribute it. In this case the  skew  between  the outputs  of the two  devices  is guaranteed to be less than 700ps.

If the product described herein is under development, significant changes to these specifications are possible. The information  in ASMP5P2309A data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance of ASMP5P2309A does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties of ASMP5P2309A related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).






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