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ASM8406C

Features: •Single power supply can operate from 2.4V through 5.5V•Internal Program ROM: 4K x 10-bit•1 sets of 18-bit DPR can access up to 256K x 10 bits data memory space•Data Registers: • 64 x 4-bit data RAM (00-1Fh plus 40h-5Fh) • Unbanked special function reg...

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SeekIC No. : 004289107 Detail

ASM8406C: Features: •Single power supply can operate from 2.4V through 5.5V•Internal Program ROM: 4K x 10-bit•1 sets of 18-bit DPR can access up to 256K x 10 bits data memory space•Dat...

ASM8406C Data Sheet

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Part Number:
ASM8406C
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

•Single power supply can operate from 2.4V through 5.5V
•Internal Program ROM: 4K x 10-bit
•1 sets of 18-bit DPR can access up to 256K x 10 bits data memory space
•Data Registers:
        • 64 x 4-bit data RAM (00-1Fh plus 40h-5Fh)
        • Unbanked special function registers (SFR) range: 20h-3Fh
•I/O Ports:
        • PRA: 4-bit I/O Port A (2Bh)
        • PRB: 2-bit Output Port B (2Dh)
•On-chip clock generator: Resistive Clock Drive(RM)
•Timer: 1
        • Timer0: a 9-bit auto-reload timer/counter
•Stack: 2-level subroutine nesting
•HALT and Release from HALT function to reduce power consumption
•Watch Dog Timer (WDT)
•Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles
•Number of instruction: 22
•The Voice function can be implemented by microprocessor instruction
       • One 8-bit COUT output for ASM8406C


Description

The ASM8406C is very low cost voice synthesizer with 4-bit microprocessor. It has various features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice synthesizer, etc. ASM8406C consists of 22 instructions in the device. With CMOS technology and halt function can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction pipeline. ASM8406C allows all instructions to be executed in a single cycle, except for program branches and data table read instructions (which need two instruction cycles).




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