Features: · Differential clock signals.
· Supports SSTL_2 class II specifications on inputs and outputs.
· Low voltage operation.
· VDD = 2.3V to 2.7V.
· Available in 114 ball BGA package.
Industrial temperature range also available.Application· DDR Memory Modules.
· Provides complete DDR DIMM logic solution with ASM5CVF857, ASM4SSTVF16857 and ASM4SSTVF16859.
· SSTL_2 compatible data registersPinout
Specifications
| Parameter |
Min |
Min |
Unit |
| Storage Temperature |
-65 |
+150 |
|
| Supply Voltage |
-0.5 |
3.6 |
V |
| Input Voltage1 |
-0.5 |
VDD + 0.5 |
V |
| Output Voltage1,2 |
-0.5 |
VDD + 0.5 |
V |
| Input Clamp Current |
± 50 |
mA
|
| Output Clamp Current |
± 50 |
mA |
| Continuous Output Current |
± 50 |
mA |
| VDD, VDDQ or GND current/pin |
100 |
mA |
| Package Thermal Impedance3 |
55 |
/W |
|
Note:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V0 > VDDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability.
|
DescriptionThe 24-Bit to 48-Bit ASM4SSTVF32852 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels except for the LVCMOS RESETB input.
Data flow of ASM4SSTVF32852 from D to Q is controlled by the differential clock (CLK/CLKB) and a control signal (RESETB). The positive edge of CLK is used to trigger the data flow,and CLKB is used to maintain sufficient noise margins,whereas the RESETB, an LVCMOS asynchronous signal is intended for use at the time of power-up only.
The ASM4SSTVF32852 supports a low power standby mode of operation. A logic "Low" level at RESETB,assures that all internal registers and outputs (Q) are reset to a logic "Low" state, and that all input receivers,data (D) buffers, and clock (CLK/CLKB) are switched off. Please note that RESETB ASM4SSTVF32852 must always be supported with a LVCMOS levels at a valid logic state since VREF may not be stable during power-up.
To ensure that outputs of ASM4SSTVF32852 are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic "Low" level during power-up.
In the DDR DIMM application, RESETB is specified to be asynchronous with respect to CLK/CLKB. Therefore,no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,the register ASM4SSTVF32852 will be cleared and the outputs will be driven to a logic "Low" level quickly relative to the time to disable the differential input receivers. This ensures there are no "glitches" on any output. However, when ASM4SSTVF32852 is coming out of low power standby state, the register will become active quickly relative to the time taken to enable the differential input receivers. When the data inputs are at a logic level "Low" and the clock of ASM4SSTVF32852 is stable during the "Low-to-High" transition of RESETB until the input receivers are fully enabled, the design ensures that the outputs will remain at a logic "Low" level.
ASM4SSTVF32852 Data Sheet
