ASM4SSTVF16857

Features:

• Fully JEDEC JC40 - JC42.5 compliant for DDR1 applications to include: PC1600, PC2100, PC2700 & PC3200 ( > JEDEC defined DDR 400 @ 200MHz )
• Low voltage operation; VDD: 2.3V - 2.7V.
• SSTL_2 Class II outputs.
• Differential clock inputs.
• Available in 48 pin TSSOP and TVSOP packages.


Application

• JEDEC and Non JEDEC DDR Memory Modules
    •Planar configurations
    •Supports PC1600 - PC2100 - PC2700 - PC3200
• SSTL_2I/O
• Provides a complete support solution for JEDEC JC42.5 (JC45) DDR I RDIMMs' when used with the ASM5CVF857 Zero Delay Buffer.


Pinout




Specifications

Parameter	Min	Max	Unit
Storage Temperature	-65	+150	°C
Supply Voltage	-0.5	3.6	V
Input Voltage1	-0.5	VDD + 0.5	V
Output Voltage1,2	-0.5	VDD + 0.5	V
Input Clamp Current	± 50		mA
Output Clamp Current	±50		mA
Continuous Output Current	±50		mA
VDD, VDDQ or GND current/pin	100		mA
Package Thermal Impedance3	55		°C/W
Note: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level V0 > VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51. These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability.

Description

The ASM4SSTVF16857 is a universal 14-bit register (D F/F based), designed for 2.3V to 2.7V VDD . The device supports SSTL_2 I/O levels, and is fully compliant with the JEDEC JC40, JC42.5 DDR I specifications covering PC1600, PC2100, PC2700, and PC3200 operational ranges. 14-bit refers to 2Q outputs of ASM4SSTVF16857 for each D input - designed for use in Stacked Registers (stacked memory devices), Buffered DIMM applications.

Data flow from D to Q is controlled by the differential clock (CLK/CLKB) along with a controlled reset (RESETB). The positive edge of CLK is used to trigger the data transfer, and CLKB is used to maintain sufficient noise margins, whereas the RESETB input of ASM4SSTVF16857 is designed and intended for use at power-up.

The ASM4SSTVF16857 supports a low power standby mode of operation. A logic low level at RESETB, assures that all internal registers and outputs (Q) are reset to a logic low state, and that all input receivers ASM4SSTVF16857, data (D) buffers, and clock (CLK/CLKB) are switched off. Note that RESETB should be supported with a LVCMOS level at a valid logic state since VREF may not be stable during power-up.

To ensure that outputs of ASM4SSTVF16857 are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic low level during power-up.

In the JEDEC defined Registered DDR DIMM application, RESETB is specified to be asynchronous with respect to CLK/CLKB; therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby mode, the register will be cleared and the outputs of ASM4SSTVF16857 will be driven to a logic low level quickly relative to the time to disable the differential input receivers. ASM4SSTVF16857 ensures there are no "glitches" on any output. However, when coming out of low power standby mode, the register will become active quickly relative to the time taken to enable the differential input receivers. When the data inputs of ASM4SSTVF16857 are at a logic level low and the clock is stable during the lowto- high transition of RESETB until the input receivers are fully enabled, the design ensures that the outputs will remain at a logic low level.