ASIC1810

Video ADC chip, R, G, B 3CHANNEL, each with 2 CHANNEL 1K * ASIC1810 8bit SRAM, SRAM WRITE CYCLE TIME 64nS, SRAM READ CYCLE TIME 32nS. 1000 pixels per line sampling point, two SRAM alternately read and write, when the line N pixel data of ASIC1810 in a SRAM, SRAM in the same section from the other N-1 line data read-out, read once, read Once, reading a total of two times, each row read cycle 30uS, there 2uS the return time; each line write cycle 64uS.

 

RIN, GIN, BIN ASIC1810 line sync frequency 15KHZ, image time 53uS, return time 11uS; by ASIC after, ROUT, GOUT, BOUT line sync frequency 30KHZ, return time 2uS.