Features: Extended Testing Over -55°C to +125° C and
Industrial Temp -40°C to 85° C
WRITE Recovery ( t / t ) t = 2 CLK
WR DPL WR
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8 or full page
Auto Precharge and Auto Refresh Modes
Self Refresh Mode (Industrial, -40°C to 85° C only)
4,096-cycle refresh
LVTTL-compatible inputs and outputs
Single +3.3V ±0.3V power supply
Longer lead TSOP for improved reliability
(OCPL*)
Short Flow / Long Flow Test Screening OptionsPinout
SpecificationsRelative to VSS ................................................... -1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to VSS ................................................... -1V to +4.6V
Operating Temperature, TA (ambient)........-55°C to +125°C
Storage Temperature (plastic) ...................-55°C to +150°C
Power Dissipation ............................................................. 1WDescriptionThe 64Mb SDRAM is a high-speed CMOS, dynamic ran- dom-access memory containing 67,108,864 bits. AS4SD4M16DG-10 is internally configured as a quad-bank DRAM with a synchronous inter- face (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16's 6,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a pro- grammed number of locations in a programmed sequence. Ac-cesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits AS4SD4M16DG-10 registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits AS4SD4M16DG-10 registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initi-ated at the end of the burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture of AS4SD4M16DG-10 is compat- ible with the 2n rule of prefetch architectures, but it also allowsthe column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide theprecharge cycles and provide seamless, high-speed, random- access operation.
The 64Mb SDRAM is designed to operate in 3.3V, low- power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances of AS4SD4M16DG-10 in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.
AS4SD4M16DG-10 Data Sheet
