AS4DDR32M16

• V_DD = +2.5V ±0.2V, V_DDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/received with data,i.e., source-synchronous data capture (has two one per byte)
• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (has twoone per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
• t_RAS lockout supported (t_RAP = t_RCD)

VDD Supply Voltage Relative to Vss ..............................-1V to +3.6V
VDDQ Supply Voltage Relative to V_SS ............................-1V to +3.6V
VREF and Inputs Voltage Relative to V_SS .......................-1V to +3.6V
I/O Pins Voltage Relative to V_SS ......................-0.5V to V_DDQ +0.5V
Operating Temperature, T_A
(ambient, Industrial) ....................................................-40 to +85
Operating Temperature, T_A
(ambient, Military) ..................................................... -55 to +125
Storage Temperature (plastic) ................................. -55 to +150
Power Dissipation...........................................................................1W
Short Circuit Output Current ..................................................... 50mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The 512Mb DDR SDRAM AS4DDR32M16 is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM.

The 512Mb DDR SDRAM AS4DDR32M16 uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512Mb DDR SDRAM effectively consists of a single 2n-bit wide, oneclock- cycle data transfer at the internal DRAM AS4DDR32M16 core and two corresponding n-bit wide, one-halfclock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS)of AS4DDR32M16 is transmitted externally,along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs.

AS4DDR32M16 offering has two data strobes, one for the lower byte and one for the upper byte.

The 512Mb DDR SDRAM AS4DDR32M16operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data of AS4DDR32M16 is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM AS4DDR32M16 are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVE command,which is then followed by a READ or WRITE command. The address bits AS4DDR32M16 registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits AS4DDR32M16 registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access.

The DDR SDRAM AS4DDR32M16 provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.

As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs AS4DDR32M16 allows for concurrent operation,thereby providing high effective bandwidth by hiding row precharge and activation time.

An auto refresh mode of AS4DDR32M16 is provided, along with a powersaving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All full drive option outputs are SSTL_2, Class II compatible.