ARM922T

The ARM922T embedded macrocell is a member of the ARM family of general-purpose 32-bit microprocessors, which offer high performance and very low power consumption.

The ARM ARM922T architecture is based on reduced instruction set computer (RISC) principles. The instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip.

Pipelining ARM922T is employed so that all parts of the processing and memory systems can operate continuously. The fivestage pipeline, utilizing a Harvard architecture consists of fetch, decode, execute, memory and write stages. The ARM922T is targeted for use at multi-programmer applications where full memory management, high performance and low power are all important. The separate data and instruction caches are 8K x 8 in size.

The macrocell ARM922T also provides a version 4 (v4) MMU to provide translation and access permission checks for
instruction and data addresses.

The ARM922T also supports the ARM debug architecture and includes logic to assist in hardware and software debug. Support is also provided on chip for coprocessors by exporting the instruction and data buses with simple handshaking signals. The ARM922T interfaces to the balance of the system over unified address and data buses, allowing implementation of either an advanced microcontroller architecture (AMBA), advanced system bus (ASB) or advanced high-performance bus (AHB) scheme either as a fully compliant AMBA bus master, or as a slave for production test. Finally, the ARM922T provides the interface to, and supports the addition of an embedded trace macrocell (ETM) for real-time tracing of instructions and data.

The processor used with the ARM922T, the ARM9TDMI, employs a unique architectural implementation known as Thumb, which makes it ideally suited to high volume applications with memory restrictions or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM9TDMI processor has two instruction sets: • A standard 32-bit ARM set • A 16-bit Thumb instruction set The Thumb set's 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM's performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65 percent of the code size of ARM, and 160 percent of the performance of an equivalent ARM processor connected to a 16-bit memory system.

A functional diagram of the ARM922T macrocell is shown in Figure 1 on page 2.