AN983B

INDUSTRY STANDARD
􀁺 IEEE802.3u 100BASE-TX and IEEE802.3 10BASE-T compliant
􀁺 Support for IEEE802.3x flow control
􀁺 IEEE802.3u Auto-Negotiation support for 10BASE-T and 100BASE-TX
􀁺 PCI Specification 2.2 compliant
􀁺 ACPI and PCI power management Ver.1.1 compliant
􀁺 Support PC99 wake on LAN

FIFO
􀁺 Provides two independent long FIFOs with 2k bytes each for transmission and receiving
􀁺 Pre-fetch up to two transmit packets to minimize inter frame gap (IFG) to 0.96us
􀁺 Retransmits collided packet without reload from host memory within 64 bytes.
􀁺 Automatically retransmits FIFO under-run packet with maximum drain threshold until 3 times retry failure and that will not influence the
        registers and transmit threshold of next packet
PCI I/F
􀁺 Provides 32-bit PCI bus master data transfer
􀁺 Supports PCI clock with frequency from 0Hz to 33MHz
􀁺 Supports network operation with PCI system clock from 20MHz to 33MHz
􀁺 Provides performance meter, PCI bus master latency timer, for tuning the threshold to enhance the performance
􀁺 Provides burst transmit packet interrupt and transmit/receive early interrupt to reduce host CPU utilization
􀁺 Supports memory-read, memory-read-line, memory-read-multiple, memory-write, memory-write-and-invalidate command while being bus
        master􀁺 
     Supports big or little endian byte orderingmemory

EEPROM/BOOT ROM I/F
􀁺 Provides write-able Flash ROM and EPROM as boot ROM with size up to 128kB
􀁺 Provides PCI to access boot ROM by byte, word, or double word
􀁺 Re-writes Flash boot ROM through I/O port by programming register􀁺
     Provides serial interface for read/write 93C46/66 EEPROM
􀁺 Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency, and Minimum-Grand from the 64 byte
        contents of 93C46/66 after PCI reset de-asserted in PCI environment.

MAC/PHYSICAL
􀁺 Integrates the whole Physical layer functions of 100BASE-TX and 10BASE-T
􀁺 Provides Full -duplex operation on both 100Mbps and 10Mbps modes
􀁺 Provides Auto-negotiation (NWAY) function of full/half duplex operation for both 10 and 100 Mbps
􀁺 Provides transmit wave-shaper, receive filters, and adaptive equalizer
􀁺 Provides MLT-3 transceiver with DC restoration for Base-line wander compensation
􀁺 Provides MAC and Transceiver (TXCVR) loop-back modes for diagnostic
􀁺 Builds in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder
􀁺 Supports external transmit transformer with turn ratio 1:1
􀁺 Supports external receive transformer with turn ratio 1:1

LED DISPLAY
􀁺 3 LEDs displays scheme provided:
􀂃    #100Mbps(on) or Speed 10(off)
􀂃    #Link (keeps on when link ok) or Activity (will be blinking with 10Hz when receiving or transmitting but not collision)
􀂃    #FD (keeps on when in Full duplex mode) or Collision (will be blinking with 20Hz when colliding)
􀁺 4 LEDs displayed scheme provided:
􀂃    #100Mbps and Link (keep on when link and 100Mpbs)
􀂃    #10Mbps and Link (keep on when link and 10Mpbs)
􀂃    #Activity (will be blinking with 10Hz when receiving or transmitting but not collision)
􀂃    #FD (keeps on when in Full duplex mode) or Collision (will be blinking with 20Hz when colliding)
MISCELLANEOUS
􀁺 Provides 128-pin QFP/LQFP packages for PCI/mini-PCI interfaces
􀁺 3.3V power supply with 5V/3.3V I/O tolerance