ApplicationThis section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register it-self does not occupy any addressable memory loca-tion. The register is composed of latches that store the commands, along with...
AM29F017D: ApplicationThis section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register it-self does not occupy any a...
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This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register it-self does not occupy any addressable memory loca-tion. The register is composed of latches that store the commands, along with the address and data informa-tion needed to execute the command. The contents of the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.
Operation | CE# | OE# | WE# | RESET# | A0A20 | DQ0DQ7 |
Read | L | L | H | H | AIN | DOUT |
Write | L | H | L | H | AIN | DIN |
CMOS Standby | Vcc± 0.5V | X | X | Vcc± 0.5V | X | High-Z |
TTL Standby | H | X | X | H | X | High-Z |
Output Disable | L | H | H | H | X | High-Z |
Hardware Reset | X | X | X | L | X | High-Z |
Temporary Sector Unprotect(See Note) | X | X | X | VID | AIN | DIN |
Optimized for memory card applications n Unlock Bypass Program Command Backwardscompatible with AM29F017D and Reduces overall programming time when AM29F017D issuing multiple program command sequencesn 5.0 V ± 10%, single power supply operation n Minimum 1,000,000 program/erase cycles per sector guaranteed - Minimizes system level power requirements n 20-year data retention at 125°C n Manufactured on 0.23 m process technology - Reliable operation for the life of the system n High performance n Package options - Access times as fast as 70 ns - 40-pin TSOP n Low power consumption - 48-pin TSOP - 25 mA typical active read current n Compatible with JEDEC standards-30 mA typical program/erase current - Pinout and software compatible with - 1 A typical standby current (standard access single-power-supply Flash standard time to active mode) - Superior inadvertent write protection n Flexible sector architecture n Data# Polling and toggle bits - Provides a software method of detecting - Any combination of sectors can be erased. program or erase cycle completion - Supports full chip erase n Ready/Busy# output (RY/BY#) - Group sector protection: - Provides a hardware method for detecting A hardware method of locking sector groups to program or erase cycle completion prevent any program or erase operations within n Erase Suspend/Erase Resume that sector group -Suspends a sector erase operation to read data Temporary Sector Group Unprotect allows code from, or program data to, a non-erasing sector, changes in previously locked sectors then resumes the erase operation n Embedded Algorithms n Hardware reset pin (RESET#) - Embedded Erase algorithm automatically preprograms and erases the entire chip or any Resets internal state machine to the read mode combination of designated sectors - Embedded Program algorithm automatically writes and verifies bytes at specified addresses