AK5368192W

Features: `8,388,608 x 36 bit organization`72 pad Single In-Line Module`Multiple CAS and RAS lines allow x18 or x36 bit widths`CAS-before-RAS, RAS-only or hidden refresh`Power7.30 Watt Max Active (60nS)6.68 Watt Max Active (70 nS)252 mW Max Standby`Operating free air temperature 0 to 70Description...

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SeekIC No. : 004279395 Detail

AK5368192W: Features: `8,388,608 x 36 bit organization`72 pad Single In-Line Module`Multiple CAS and RAS lines allow x18 or x36 bit widths`CAS-before-RAS, RAS-only or hidden refresh`Power7.30 Watt Max Active (6...

floor Price/Ceiling Price

Part Number:
AK5368192W
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

`8,388,608 x 36 bit organization
`72 pad Single In-Line Module
`Multiple CAS and RAS lines allow x18 or x36 bit widths
`CAS-before-RAS, RAS-only or hidden refresh
`Power
7.30 Watt Max Active (60nS)
6.68 Watt Max Active (70 nS)
252 mW Max Standby
`Operating free air temperature 0 to 70





Description

The Accutek AK5368192W high density memory module is a CMOS dynamic RAM organized in 8192K x 36 bit words. The module consists of sixteen standard 4 Meg x 4 DRAMs and eight 4 Meg x 1 DRAMs, each in plastic SOJ packages. The assembly has 14 drams mounted on the front side and 10 drams mounted on the back side of a printed circuit board in a 72 pad leadless SIM configuration.

This configuration of AK5368192W allows socket-mounting of large quantities of memory in applications where high density and ease of inserting additional memory are important.

The operation of the AK5368192W is identical to sixteen 4Mx 4 plus eight 4M x 1 Drams. There are fourCAS lines and four RAS lines. On each bank of 4M x 36, independent byte control is accomplished by fourCAS lines. Each separateCAS line controls two 4M x 4 Drams along with a 4Mx 1 Dram with data in tied to data out to form a 9 bit byte. Two banks of 36 bits are controlled by the two pairs of RAS lines. An eighteen bit data path can be produced by connecting DQ0 to DQ18, DQ1 to DQ19, etc. and alternately strobing RAS0 with RAS1 and RAS2 with RAS3.






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