AK5364096W

Features: 4,194,304 x 36 bit organization Low profile board height of 0.875 inch 72 pad Single In-Line Module MultipleCAS andRAS lines allow x18 or x36 bit widths Power:7.92 Watt Max Active (60nS)6.60 Watt Max Active (70 nS)66 mW Max StandbyCAS-before-RAS, RAS-only or hidden refreshDescriptionThe...

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SeekIC No. : 004279390 Detail

AK5364096W: Features: 4,194,304 x 36 bit organization Low profile board height of 0.875 inch 72 pad Single In-Line Module MultipleCAS andRAS lines allow x18 or x36 bit widths Power:7.92 Watt Max Active (60nS)6...

floor Price/Ceiling Price

Part Number:
AK5364096W
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

4,194,304 x 36 bit organization
Low profile board height of 0.875 inch
72 pad Single In-Line Module
MultipleCAS andRAS lines allow x18 or x36 bit widths
Power:
7.92 Watt Max Active (60nS)
6.60 Watt Max Active (70 nS)
66 mW Max Standby
CAS-before-RAS, RAS-only or hidden refresh





Description

The Accutek AK5364096W high density memory module is a CMOS Dynamic RAM organized in 4096K x 36 bit words. The AK5364096W module consists of eight standard 4 Meg x 4 DRAMs and four 4 Meg x 1 DRAMs in plastic SOJ packages. The 4 Meg x 4 DRAMs are mounted on the front surface and the 4 Meg x 1 parity DRAMs are mounted on the back surface of a printed circuit board with a low profile height of only 0.875" in a 72 pin leadless SIM configuration. This configuration allows socket-mounting of large quantities of memory in applications where high density and ease of inserting additional memory are important.

The operation of the AK5364096W is identical to eight 4Meg x 4 plus four 4Meg x 1 DRAMs. There are fourCAS lines and two RAS lines. Independent byte control is accomplished by fourCAS lines. Each separateCASline controls two 4Meg x 4 DRAMs, along with a 4Meg x 1 DRAM with data in tied to data out to form a 9 bit byte. The bank of 36 bits is controlled by the twoRAS lines. An eighteen bit data path can be produced by connecting DQ0 to DQ18, DQ1 to DQ19, etc. and alternately strobing RAS0 with RAS2.






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