Features: GENERAL:• Conforms to the ISO/IEC-CD 13818-1 MPEG-II transport layer protocol and Digital Video Broadcasting (DVB)FEC specification• Viterbi decoded data rates up to 62 Mbits/sec at any code rate• Programmable block size from 34 to 255 bytes• Multiplexed parallel ...
AHA4210: Features: GENERAL:• Conforms to the ISO/IEC-CD 13818-1 MPEG-II transport layer protocol and Digital Video Broadcasting (DVB)FEC specification• Viterbi decoded data rates up to 62 Mbits/s...
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Features: ENCODER: • Clock and Data Serial Input, or 8-bit Parallel • 172 Mbits/sec ch...
ABSOLUTE MAXIMUM STRESS RATINGS | |||||
SYMBOL |
CHARACTERISTICS |
MIN |
MAX |
UNITS |
TEST CONDITIONS |
Tstg |
Storage temperature |
-55 |
150 |
||
Vdd |
Supply voltage |
-0.5 |
6.0 |
V |
|
Vin |
Input voltage |
Vss-0.5 |
Vdd+0.5 |
V |
|
Package: 68 pin PLCC |
The AHA4210, referred to as the RSVP, is a single-chip Forward Error Correction LSI device combining a Viterbi decoder, a Reed-Solomon decoder, a descrambler (energy dispersal) and a deinterleaver. The AHA4210 conforms to the MPEG-II transport layer protocol specified by ISO/IEC standard and FEC requirements of Digital Video Broadcasting (DVB) DT/8622/DVB and DT/8610/ III-B specification. These documents are referred to as the DVB specification.
The Viterbi decoder supports selectable code rates of 1/2, 2/3, 3/4, 5/6, 6/7 or 7/8 using industry standard puncturing algorithms. Viterbi decoded data rate is up to 62 Mbits/second at all code rates. The chip also performs byte alignment and block/ packet synchronization detecting sync bytes used in transmission. The descrambling function is selectable with a programmable seed or performed externally. Each functional block of AHA4210 may be bypassed giving more flexibility to a system designer.
Block size programmability, several code rate choices and programmable RS error correction capability of AHA4210 allows flexibility to a digital communications system designer incorporating Forward Error Correction into a receiver. Intel 80C188 multiplexed parallel or serial I2C protocol interface allows the system microprocessor to program internal registers and monitor channel performance.
This AHA4210 document contains key features, correction terms, functional description, signal functions, Related Technical Publications, DC and AC characteristics, pinout, package dimension and ordering information.