AFS090

Features:

• ADC Conversions Controlled by MCU/MPU Writes
• AMBA APB Slave Interface (8- or 16-Bit Data Widths Supported)
• 14 Maskable Interrupt Sources
• Internal Clock Divider for Generating Analog Configuration MUX Clock
• Optional Read FIFO Stores up to 256 ADC Conversion Results
• Analog Configuration MUX Can Be Configured by SmartGen

Description

CoreAI (Analog Interface) allows for simple control of the analog peripherals within the Fusion family of Actel AFS090 devices. Control may be implemented with an internal or external microprocessor or microcontroller (such as Core8051 or CoreMP7), or with user-created custom logic within the FPGA fabric. The industry-standard AMBA (Advanced Microcontroller Bus Architecture) APB (Advanced Peripheral Bus) slave interface is used as the primary control mechanism within CoreAI in AFS090.

CoreAI instantiates the AB (Analog Block) macro, as shown in Figure 1 on page 2. The AB macro includes the ACM (Analog Configuration MUX) interface, Analog Quads, and RTC (Real-Time Counter). The ACM interface, within the AB macro, is used to control configuration of the Analog Quads and RTC in the Fusion device. CoreAI generates the control signals used by the ACM, including its clock signal, which is generated by an internal clock divider. The ACM clock divider is used to ensure that the ACM interface is clocked at a frequency less than or equal to 10 MHz (refer to "ACM Interface" on page 18 for details). For more details on the silicon features of the AFS090, such as the Analog Quads, RTC, or ACM, refer to the Fusion datasheet.

Several aspects of CoreAI can be configured using toplevel parameters (Verilog) or generics (VHDL). For a detailed description of the parameters/generics, refer to Table 4 on page 6. The CoreAI block diagram of AFS090 is shown in Figure 1. A typical application using CoreAI is shown in Figure 2.

AFS090 Benefits
High-Performance Reprogrammable Flash
Technology
• Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Nonvolatile, Retains Program when Powered Off
• Live at Power-Up (LAPU) Single-Chip Solution
• 350 MHz System Performance
Embedded Flash Memory
• User Flash Memory 2 Mbits to 8 Mbits
Configurable 8-, 16-, or 32-Bit Datapath
10 ns Access in Read-Ahead Mode
• 1 kbit of Additional FlashROM
Integrated A/D Converter (ADC) and Analog I/O
• Up to 12-Bit Resolution and up to 600 ksps
• Internal 2.56 V or External Reference Voltage
• ADC: Up to 30 Scalable Analog Input Channels
• High-Voltage Input Tolerance: 10.5 V to +12 V
• Current Monitor and Temperature Monitor Blocks
• Up to 10 MOSFET Gate Driver Outputs
P- and N-Channel Power MOSFET Support
Programmable 1, 3, 10, 30 A and 20 mA Drive Strengths
• ADC Accuracy is Better than 1%
On-Chip Clocking Support
• Internal 100 MHz RC Oscillator (accurate to 1%)
• Crystal Oscillator Support (32 kHz to 20 MHz)
• Programmable Real-Time Counter (RTC)
• 6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated
PLLs
Phase Shift, Multiply/Divide, and Delay Capabilities
Frequency: Input 1.5350 MHz, Output 0.75350 MHz
Low Power Consumption
• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
• Sleep and Standby Low Power Modes
In-System Programming (ISP) and Security
• Secure ISP with 128-Bit AES via JTAG
• FlashLock® to Secure FPGA Contents
Advanced Digital I/O
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages Up to 5 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
Built-In I/O Registers
700 Mbps DDR Operation
• Hot-Swappable I/Os
• Programmable Output Slew Rate, Drive Strength, and Weak
Pull-Up/Down Resistor
• Pin-Compatible Packages across the Fusion Family
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (*1, *2, *4, *9,
and *18 organizations available)
• True Dual-Port SRAM (except *18)
• Programmable Embedded FIFO Control Logic
Soft ARM7™ Core Support in M7 and M1 Fusion Devices
• ARM Cortex™-M1 (without debug), CoreMP7Sd