Features: `E1, T1, AND SUBRATE OPERATION`COMPLIES WITH G.SHDSL AND HDSL2`16-BIT, DELTA-SIGMA CONVERTERS`ON-CHIP DRIVER AND PGA`PROGRAMMABLE tx AND rx FILTERS`SERIAL DIGITAL INTERFACE`750mW POWER DISSIPATION AT E1`+5V POWER (5V OR 3.3V DIGITAL)`SSOP-28 PACKAGE`40°C TO +85°C TEMPERATURE RANGEPinoutS...
AFE1230: Features: `E1, T1, AND SUBRATE OPERATION`COMPLIES WITH G.SHDSL AND HDSL2`16-BIT, DELTA-SIGMA CONVERTERS`ON-CHIP DRIVER AND PGA`PROGRAMMABLE tx AND rx FILTERS`SERIAL DIGITAL INTERFACE`750mW POWER DIS...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Texas Instrument's analog front-end chip, the AFE1230, is designed to greatly reduce the size and cost of G.SHDSL and HDSL2 application designs. It provides a transceiver as the line interface between the Digital Signal Processor (DSP) and the local loop. The AFE1230 is designed to handle upstream and downstream data transmission over a wide range of data rates from 64kbps to 2.5Mbps. Functionally, this unit consists of a transmitter and receiver section.
The transmitter section consists of a digital interpolation filter, a 16-bit, delta-sigma Digital-to-Analog (D/A) converter, a digitally programmable fifth-order or seventh-order SC (Switched Capacitor) low-pass filter, and a differential output line driver. The receiver section of AFE1230 includes an input Programmable Gain Amplifier (PGA), a 16-bit, delta-sigma Analog-to-Digital (A/D) converter, and a programmable decimation filter.
The AFE1230 receives a 16-bit data word plus an 8-bit control byte via the serial interface to facilitate the D/A conversion and control functions. The subsequent analog signal is sent to the on-chip line driver that provides 14.5dBm power into a 135Ω line for G.SHDSL operation. In addition, the on-chip line driver can be used as an output buffer with an external line driver, such as the OPA2677, to generate over 17dBm power into a 135Ω line for HDSL2 operation. With an appropriate DSP, the transmitted Power Spectral Density (PSD) complies with either the G.SHDSL standard or with the HDSL2 standard (via an OPA2677 used as an external driver). In the receive path, the input amplifier sums the signals from the line and hybrid path to perform first-order analog echo cancellation.
The resultant signal is then digitized by the rest of the receive section into a 16-bit digital word that is sent to the external DSP. This AFE1230 IC operates on a single 5V supply, while the digital supply can be from 3.3V to 5V. It is housed in a SSOP-28 package. The typical power consumption is 750mW at E1 rates with G.SHDSL (560mW for HDSL2 operation) and an operation temperature range of 40°C to +85°C.