Features: Meets SONET requirements for jittertransfer/generation/tolerance
Quantizer sensitivity: 4 mV typical
Adjustable slice level: ±100 mV
1.9 GHz minimum bandwidth
Patented clock recovery architecture
Loss of signal detect range: 3 mV to 15 mV
Single reference clock frequency for all rates, including 15/14 (7%) wrapper rate
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz
REFCLK
LVPECL/LVDS/LVCMOS/LVTTL compatible inputs
(LVPECL/LVDS only at 155.52 MHz)
19.44 MHz oscillator on-chip to be used with external crystal
Loss of lock indicator
Loopback mode for high speed test data
Output squelch and bypass features
Single-supply operation: 3.3 V
Low power: 540 mW typical
7 mm × 7 mm 48-lead LFCSP ApplicationSONET OC-3/-12/-48, SDH STM-1/-4/-16, GbE and 15/14FEC rates
WDM transponders
Regenerators/repeaters
Test equipment
Backplane applications Pinout
Specifications
| Data Rate (Gb/s) |
2.7Gbps |
| Voltage Supply (V) |
+3.3V |
| Power Dissipation (mW) |
500mW |
| Package |
7x7 mm LFCSP |
| Jitter Tolerance (Ulpp) |
1.0 @ 1 MHz |
| Jitter Gen (mUI rms) |
2 |
| Input Sensitivity (mVp-p) |
4mV p-p |
| Rate |
Multi |
| Reference Clk |
X |
DescriptionThe ADN2819 provides receiver functions of Quantization, Signal Level Detect and Clock and Data Recovery at rates of OC-3, OC-12, Gigabit Ethernet, OC-48 and all FEC rates. All SONET jitter
The ADN2819 provides the receiver functions of quantization,signal level detect, and clock and data recovery at rates of OC-3,OC-12, OC-48, Gigabit Ethernet, and 15/14 FEC rates. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for 40°C to +85°C ambient temperature, unless otherwise noted. The device is intended for WDM system applications, and can be used with either an external reference clock or an on-chip oscillator with external crystal. Both native rates and 15/14 rate digital wrappers are supported by the ADN2819, without any change of reference clock.
This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power, fiber optic receiver. The receiver front end signal detect circuit indicates when the input signal level has fallen below a user-adjustable threshold. The signal detect circuit has hysteresis toprevent chatter at the output. The ADN2819 is available in a compact 7 mm * 7 mm, 48-lead chip scale package.
ADN2819 Data Sheet
