ADM4851

The ADM4850−ADM4857 are differential line transceivers suitable for high speed half- and full-duplex data communication on multipoint bus transmission lines. They are designed for balanced data transmission and comply with EIA Standards RS-485 and RS-422. The ADM4850−ADM4853 are half-duplex transceivers, which share differential lines and have separate enable inputs for the driver and receiver. The full-duplex ADM4854−ADM4857 transceivers have dedicated differential line driver outputs and receiver inputs.

The parts of ADM4850−ADM4857 have a 1/8-unit-load receiver input impedance, which allows up to 256 transceivers on one bus. Since only one driver should be enabled at any time, the output of a disabled or pow-ered-down driver is three-stated to avoid overloading the bus.

The ADM4850−ADM4857  receiver inputs have a true fail-safe feature, which ensures a logic high output level when the inputs are open or shorted. This guarantees that the receiver outputs are in a known state before communication begins and when communication ends.

The ADM4850−ADM4857  driver outputs are slew-rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses. Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit.

The parts of ADM4850−ADM4857  are fully specified over the commercial and industrial temperature ranges, and are available in 8-lead SOIC and LFCSP packages.