ADM483

The ADM483 is a low power differential line transceiver suitable for half-duplex data communication on multipoint bus trans-mission lines. It is designed for balanced data transmission, and complies with EIA Standards RS-485 and RS-422.The part contains a differential line driver and a differential line receiver. Both share the same differential pins, with either the driver or the receiver being enabled at any given time.

The ADM483 has an input impedance of 12 kΩ, allowing up to 32 transceivers on one bus. Since only one driver should be enabled at any time, the output of a disabled or powered-down driver is three-stated to avoid overloading the bus. This high impedance driver output is maintained over the entire common-mode voltage range from 7 V to +12 V.

The ADM483 receiver contains a fail-safe feature that results in a logic high output state if the inputs are unconnected (floating).

The driver outputs are slew-rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses. Excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. The part of ADM483 is fully specified over the industrial temperature range, and is available in an 8-lead SOIC package.