ADC14DS105CISQ

Supply Voltage (V_A, V_DR)...............−0.3V to 4.2V
Voltage on Any Pin (Not to exceed 4.2V)....−0.3V to (V_A +0.3V)
Input Current at Any Pin other than Supply Pins (Note 4)..±5 mA
Package Input Current (Note 4) ..............±50 mA
Max Junction Temp (T_J) ................... +150
Thermal Resistance (_JA)..................30/W
ESD Rating
   Human Body Model (Note 6) ................2500V
   Machine Model (Note 6)................... 250V
Storage Temperature ...............−65 to +150

Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 7)

The ADC14DS105CISQ and ADC14DS105AISQ are highperformance CMOS analog-to-digital converters capable of converting two analog input signals into 14-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). The digital outputs are serialized and provided on differential LVDS signal pairs. Both parts of ADC14DS105CISQ and ADC14DS105AISQ provide excellent performance, however, the ADC14DS105AISQ offers higher SFDR. These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. The ADC14DS105 may be operated from a single +3.0V or 3.3V power supply. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC14DS105 can be operated with an external 1.2V reference. The selectable duty cycle stabilizer maintains performance over a wide range of clock duty cycles. A serial interface allows access to the internal registers for full control of the ADC14DS105's functionality. The ADC14DS105 is available in a 60-lead LLP package and operates over the industrial temperature range of −40 to +85.