Features: ·1 GHz Full Power Bandwidth
·Internal reference and sample-and-hold circuit
·Low power consumption
·Data Ready output clock
·Clock Duty Cycle Stabilizer
·Single +3.0V or +3.3V supply operation
·Power-down mode
·32-pin LLP package, (5x5x0.8mm, 0.5mm pin-pitch)Application· High IF Sampling Receivers
· Wireless Base Station Receivers
· Test and Measurement Equipment
· Communications Instrumentation
· Portable InstrumentationPinout
Specifications
| Resolution |
12 bits |
| Channels |
1 Channels |
| SNR |
70.1 dB |
| SFDR |
90 dB |
| ENOB |
11.3 bits |
| Max Sample Rate |
105 MSPS |
| Min Sample Rate |
20 MSPS |
| Power Dissipation |
0.4 Watt |
| PowerWise Rating 1 |
1.51 pJ/conv |
| INL (+/-) |
0.5 LSB |
| SINAD |
70 dB |
| DNL (+/-) |
0.25 LSB |
| THD dB |
-88 dB |
| Min Supply Voltage |
3 Volt |
| Max Supply Voltage |
3.6 Volt |
| Nominal Vin |
2 Vpp |
| Temperature Min |
-40 deg C |
| Temperature Max |
85 deg C |
| Data Converter Type |
ADC |
| Automotive Selection Guide |
Yes |
| PowerWise |
Yes |
| View Using Catalog |
Supply Voltage (VA, VDR) .....−0.3V to 4.2V
Voltage on Any Pin
(Not to exceed 4.2V).... −0.3V to (VA +0.3V)
Input Current at Any Pin other
than Supply Pins (Note 4)........ ±5 mA
Package Input Current (Note 4).... ±50 mA
Max Junction Temp (TJ).......... +150
Thermal Resistance (JA)........ 30 /W
ESD Rating
Human Body Model (Note 6) ....... 2500V
Machine Model (Note 6) ..........250V
Storage Temperature...... −65 to +150
Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging.
DescriptionThe ADC12C105 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC12C105 may be operated from a single +3.0V or +3.3V power supply and consumes low power.
A separate +2.5V supply may be used for the digital output interface which allows lower power operation with reduced noise. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC12C105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles.
The ADC12C105 is available in a 32-lead LLP package and operates over the industrial temperature range of −40°C to +85°C.
Reliability Metrics
| Part Number |
Process |
EFR Reject |
EFR Sample Size |
PPM |
LTA Rejects |
LTA Device Hours |
FITS |
MTTF (Hours) |
| ADC12C105CISQX |
CMOS9 |
1 |
6382 |
157 |
0 |
923000 |
4 |
261903770 |
Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.For more information on Reliability Metrics, please click here.
Design Tools
| Title |
Size in Kbytes |
Date |
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| Evaluation Systems |
32 Kbytes |
2-Jun-2008 |
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ADC12C105 Data Sheet
