PinoutSpecificationsResolution10 bitsChannels2 ChannelsSNR57 dBSFDR66 dBENOB9.1 bitsMax Sample Rate1000 MSPSMin Sample Rate200 MSPSPower Dissipation2.77 WattPowerWise Rating 12.52 pJ/convDNL (+/-)0.25 LSBINL (+/-)0.65 LSBSINAD56.5 dBTHD dB-66 dBMin Supply Voltage1.8 VoltMax Supply Voltage2.0 VoltN...
ADC10D1000: PinoutSpecificationsResolution10 bitsChannels2 ChannelsSNR57 dBSFDR66 dBENOB9.1 bitsMax Sample Rate1000 MSPSMin Sample Rate200 MSPSPower Dissipation2.77 WattPowerWise Rating 12.52 pJ/convDNL (+/-)0....
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Resolution | 10 bits |
Channels | 2 Channels |
SNR | 57 dB |
SFDR | 66 dB |
ENOB | 9.1 bits |
Max Sample Rate | 1000 MSPS |
Min Sample Rate | 200 MSPS |
Power Dissipation | 2.77 Watt |
PowerWise Rating 1 | 2.52 pJ/conv |
DNL (+/-) | 0.25 LSB |
INL (+/-) | 0.65 LSB |
SINAD | 56.5 dB |
THD dB | -66 dB |
Min Supply Voltage | 1.8 Volt |
Max Supply Voltage | 2.0 Volt |
Nominal Vin | .79 Vpp |
Temperature Min | -40 deg C |
Temperature Max | 85 deg C |
Data Converter Type | ADC |
AEC Q-100 Automotive Grade | 0 |
Automotive Selection Guide | Yes |
PowerWise | Yes |
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The ADC10D1000 is the latest advance in National's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0 GSPS (Non-DES Mode) or for a single channel up to 2.0 GSPS (DES Mode). The ADC10D1000 achieves excellent accuracy and dynamic performance while dissipating less than 2.8 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package which does not require a heat sink over the rated industrial temperature range of
The ADC10D1000 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization,
Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes.
Reliability Metrics
Part Number | Process | EFR Reject | EFR Sample Size | PPM | LTA Rejects | LTA Device Hours | FITS | MTTF (Hours) |
ADC10D1000CIUT | CMOS9 | 1 | 6382 | 157 | 0 | 923000 | 4 | 261903770 |