Features: PLL generated or direct master clockLow EMI design108 dB DAC/107 dB ADC dynamic range and SNR−94 dB THD + NSingle 3.3 V supplyTolerance for 5 V logic inputsSupports 24 bits and 8 kHz to 192 kHz sample ratesDifferential ADC inputSingle-ended DAC outputLog volume control with autoram...
ADAU1328: Features: PLL generated or direct master clockLow EMI design108 dB DAC/107 dB ADC dynamic range and SNR−94 dB THD + NSingle 3.3 V supplyTolerance for 5 V logic inputsSupports 24 bits and 8 kHz...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Analog (AVDD).................................−0.3 V to +3.6 V
Digital (DVDD)..................................−0.3 V to +3.6 V
Input Current (Except Supply Pins)...............±20 mA
Analog Input Voltage (Signal Pins)...0.3 V to AVDD + 0.3 V
Digital Input Voltage (Signal Pins).....−0.3 V to DVDD + 0.3 V
Operating Temperature Range (Case)......−40°C to +85°C
Storage Temperature Range...................−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
The ADAU1328 is a high performance, single-chip codec that provides two analog-to-digital converters (ADCs) with differential input and eight digital-to-analog converters (DACs) with single-ended output using the Analog Devices, Inc. patented multibit sigma-delta (-) architecture. An SPI port is included,allowing a microcontroller to adjust volume and many other parameters. The ADAU1328 operates from 3.3 V digital and analog supplies. The ADAU1328 is available in a 48-lead (single-ended output) LQFP. Other members of this family include a differential DAC output and I2C® control port version.
The ADAU1328 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures.By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, the ADAU1328 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The digital-to-analog and analog-to-digital converters are designed using the latest ADI continuous time architectures to further minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions.