AD9600

The AD9600 is a dual, 10-bit, 105 MSPS/125 MSPS/150 MSPS ADC. It is designed to support communications applications where low cost, small size, and versatility are desired.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

Features of the AD9600 are:(1)SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS; (2)SFDR = 81 dBc to 70 MHz at 150 MSPS; (3)low power: 825 mW at 150 MSPS; (4)1.8 V analog supply operation; (5)1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply; (6)integer 1 to 8 input clock divider; (7)intermediate frequency (IF) sampling frequencies up to 450 MHz; (8)internal analog-to-digital converter (ADC) voltage reference; (9)Integrated ADC sample-and-hold inputs; (10)flexible analog input: 1 V p-p to 2 V p-p range; (11)differential analog inputs with 650 MHz bandwidth; (12)ADC clock duty cycle stabilizer; (13)95 dB channel isolation/crosstalk; (14)serial port control; (15)user-configurable built-in self-test (BIST) capability; (16)energy-saving power-down modes.

The absolute maximum ratings of the AD9600 can be summarized as:(1)AVDD,DVDD to AGND:-0.3 V to +2.0 V;(2)storage temperature range:-65 to +150;(3)DRVDD to DRGND:-0.3 V to +3.9 V;(4)junction temperature:+150;(5)SYNC to AGND:-0.3 V to +3.9 V;(6)VREF to AGND:-0.3 V to AVDD + 0.2 V.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied.Exposure to absolute maximum rating conditions for extended periods may affect device reliability.The AD9600 architecture consists of a dual front-end sampleand-hold amplifier (SHA) followed by a pipelined switchedcapacitor ADC.The quantized outputs from each stage are combined into a final 10-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock.

The dual ADC core