AD9201

Features:

Complete Dual Matching ADCs
Low Power Dissipation: 215 mW (+3 V Supply)
Single Supply: 2.7 V to 5.5 V
Differential Nonlinearity Error: 0.4 LSB
On-Chip Analog Input Buffers
On-Chip Reference
Signal-to-Noise Ratio: 57.8 dB
Over Nine Effective Bits
Spurious-Free Dynamic Range: 73 dB
No Missing Codes Guaranteed
28-Lead SSOP




Pinout






Specifications

AVDD AVSS 0.3 +6.5 V
DVDD DVSS 0.3 +6.5 V
AVSS DVSS0.3 +0.3 V
AVDDDVDD6.5 +6.5 V
CLKAVSS 0.3 AVDD + 0.3 V
Digital Outputs DVSS0.3 DVDD + 0.3 V
AINA, AINB AVSS1.0 AVDD + 0.3 V
VREF AVSS 0.3 AVDD + 0.3 V
REFSENSE AVSS 0.3 AVDD + 0.3 V
REFT, REFB AVSS0.3 AVDD + 0.3 V




Description

The AD9201 is a complete dual channel, 20 MSPS, 10-bit CMOS ADC. The AD9201 is optimized specifically for applications where close matching between two ADCs is required (e.g., I/Q channels in communications applications). The 20 MHz sampling rate and wide input bandwidth will cover both narrow- band and spread-spectrum channels. The AD9201 integrates two 10-bit, 20 MSPS ADCs, two input buffer amplifiers, an internal voltage reference and multiplexed digital output buffers.

Each ADC incorporates a simultaneous sampling sample-and-hold amplifier at its input. The analog inputs are buffered; no external input buffer op amp will be required in most applications. The ADCs are implemented using a multistage pipeline architecture that offers accurate performance and guarantees no
missing codes. The outputs of the ADCs are ported to a multiplexed digital output buffer. The AD9201 is manufactured on an advanced low cost CMOS
process, operates from a single supply from 2.7 V to 5.5 V, and consumes 215 mW of power (on 3 V supply). The AD9201 input structure accepts either single-ended or differential signals, providing excellent dynamic performance up to and beyond its 10 MHz Nyquist input frequencies.