Features: Programmable low and high gain (<2 dB resolution)Low range: −11 dB to +17 dBHigh range: +6 dB to +34 dBDifferential input and output:200 differential input100 differential output7 dB noise figure @ maximum gainTwo-tone IP3 of +35 dBm @ 70 MHz−3 dB bandwidth of 750 MHz40 ...
AD8370: Features: Programmable low and high gain (<2 dB resolution)Low range: −11 dB to +17 dBHigh range: +6 dB to +34 dBDifferential input and output:200 differential input100 differential outpu...
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Programmable low and high gain (<2 dB resolution)
Low range: −11 dB to +17 dB
High range: +6 dB to +34 dB
Differential input and output:
200 differential input
100 differential output
7 dB noise figure @ maximum gain
Two-tone IP3 of +35 dBm @ 70 MHz
−3 dB bandwidth of 750 MHz
40 dB precision gain range
Serial 8-bit digital interface
Wide input dynamic range
Power-down feature
Single 3 V to 5 V supply
Pin No. | Mnemonic | Description |
1 | INHI | Balanced Differential Input. Internally biased. |
2,15 | ICOM | Input Common. Connect to a low impedance ground. This node is also connected to the exposed pad on the bottom of the device. |
3 | VCCI | Input Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed. |
4 | PWUP | Power Enable Pin. Device is operational when PWUP is pulled high. |
5 | VOCM | Common-Mode Output Voltage Pin. The midsupply ((VVCCO − VOCOM)/2) common-mode voltage is delivered to this pin for external bypassing for additional common-mode supply decoupling. This can be achieved with a bypass capacitor to ground. This pin is an output only and is not to be driven externally. |
6,11 | VCCO | Output Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed. |
7,10 | OCOM | Output Common. Connect to a low impedance ground. |
8 | OPHI | Balanced Differential Output. Biased to midsupply. |
9 | OPLO | Balanced Differential Output. Biased to midsupply. |
12 | LTCH | Serial Data Latch Pin. Serial data is clocked into the shift register via the DATA pin when LTCH is low. Data in shift register is latched on the next high-going edge. |
13 | CLCK | Serial Clock Input Pin. |
14 | DATA | Serial Data Input Pin. |
15 | INLO | Balanced Differential Input. Internally biased. |
Gain Control | Digital |
-3 dB BW (MHz) | 700MHz |
Gain Low End (dB) | +25dB |
Gain High End (dB) | +34dB |
Number of Channels | 1 |
Spectral Noise (nV/rtHz) | 2.1nV/rtHz |
Supply Voltage (V) | +5.5V |
Supply Current | 78mA |
Parameter | Rating |
Supply Voltage, VS | 5.5 V |
PWUP, DATA, CLCK, LTCH | VS + 500 mV |
Differential Input Voltage, |
2 V |
Common-Mode Input Voltage, VINHI or |
VS + 500 mV |
Internal Power Dissipation | 575 mW |
JA (Exposed paddle soldered down) | 30°C/W |
JA (Exposed paddle not soldered down) | 95°C/W |
JC (At exposed paddle) | 9°C/W |
Maximum Junction Temperature | 150°C |
Operating Temperature Range | 40°C to +85°C |
Storage Temperature Range | 65°C to +150°C |
Lead Temperature Range (Soldering 60 sec) |
235°C |