AD7849

V_DD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 V to +17 V
V_CC to DGND² . . . . . . . . . . . . . . . . . . 0.4 V, V_DD + 0.4 V or
+7 V (Whichever Is Lower)
V_SS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 V to 17 V
V_REF+ to DGND . . . . . . . . . . . . . . . . V_DD + 0.4 V, V_SS 0.4 V
V_REF to DGND . . . . . . . . . . . . . . . . V_DD + 0.4 V, V_SS 0.4 V
V_OUT to DGND³ . . . . . . . . . . . . . .V_DD + 0.4 V, V_SS 0.4 V or
±10 V (Whichever Is Lower)
R_OFS to DGND . . . . . . . . . . . . . . . . . V_DD + 0.4 V, V_SS 0.4 V
Digital Input Voltage to DGND . . . . . . 0.4 V to V_CC + 0.4 V
Input Current to any Pin Except Supplies4 . . . . . . . . . ±10 mA
Operating Temperature Range
Commercial/Industrial (A, B, C Versions). . . . 40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . 55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . . 875 mW
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 102°C/W
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . +260°C
SOP Package, Power Dissipation . . . . . . . . . . . . . . . . 875 mW
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . ..74°C/W
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . 875 mW
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 71°C/W
Lead Temperature, Soldering (Soldering 10 secs) . . . 260°C

NOTES
¹Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
²V_CC must not exceed V_DD by more than 0.4 V. If it is possible for this to happen during power-up or power-down (for example, if V_CC is greater than +0.4 V while V_DD is still 0 V), the following diode protection scheme will ensure rotection.
³V_OUT may be shorted to DGND, +10 V, 10 V, provided that the power dissipation of the package is not exceeded.
⁴Transient currents of up to 100 mA will not cause SCR latch-up.

The AD7849 is a 14-bit/16-bit serial input multiplying DAC. The DAC architecture ensures excellent differential linearity performance, and monotonicity is guaranteed to 14 bits for the A grade and to 16 bits for all other grades over the specified temperature ranges.

During power-up and power-down sequences (when the supply voltages are changing), the V_OUT pin is clamped to 0 V via a low impedance path. To prevent the output of A3 being shorted to 0 V during this time, transmission gate G1 is also opened. These conditions are maintained until the power supplies stabilize and a valid word is written to the DAC register. At this time, G2 opens and G1 closes. Both transmission gates are also externally controllable via the Reset In (RST IN) control input. For instance, if theRST IN input is driven from a battery supervisor chip, then on power-off or during a brown out, theRST IN input will be driven low to open G1 and close G2. The DAC must be reloaded, withRST IN high, to re-enable the output. Conversely, the on-chip voltage detector output (RST OUT) is also available to the user to control other parts of the system.

The AD7849 has a versatile serial interface structure and can be controlled over three lines to facilitate opto-isolator applications.

SDOUT is the output of the on-chip shift register and can be used in a daisy-chain fashion to program devices in the multichannel system. The DCEN (Daisy Chain Enable) input controls this function.

The BIN/COMP pin sets the DAC coding; with BIN/COMP set to 0, the coding is straight binary; and with it set to 1, the coding is 2s complement. This allows the user to reset the DAC to 0 V in both the unipolar and bipolar output ranges.

The part is available in a 20-lead DIP and 20-lead SOIC package.