Features: ·Two 12-Bit DACs in One Package
·DAC Ladder Resistance Matching: 0.5%
·Space Saving Skinny DIP and Surface Mount Packages
·4-Quadrant Multiplication
·Low Gain Error (1 LSB max Over Temperature)
·Byte Loading Structure
·Fast Interface TimingApplication·Automatic Test Equipment
·Programmable Filters
·Audio Applications
·Synchro Applications
·Process ControlSpecificationsVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +17 V
VREFA, VREFB to AGNDA, AGNDB . . . . . . . . . . . . . . ±25 V
VRFBA, VRFBB to AGNDA, AGNDB . . . . . . . . . . . . . . ±25 V
Digital Input Voltage to DGND . . . . . 0.3 V, VDD +0.3 V
IOUTA, IOUTB to DGND . . . . . . . . . . . 0.3 V, VDD +0.3 V
AGNDA, AGNDB to DGND . . . . . . . . . 0.3 V, VDD +0.3 V
Power Dissipation (Any Package)
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450 mW
Derates Above +75°C . . . . . . . . . . . . . . . . . . .6 mW/°C
Operating Temperature Range
Commercial Plastic (J, K, L Versions) . 40°C to +85°C
Industrial Hermetic (A, B, C Versions) .40°C to +85°C
Extended Hermetic (S, T, U Versions) 55°C to +125°C
Storage Temperature . . . . . . . . . . . . 65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . +300°C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DescriptionThe AD7537 contains two 12-bit current output DACs on one monolithic chip. A separate reference input is provided for each DAC. The dual DAC saves valuable board space, and the monolithic construction ensures excellent thermal tracking. Both DACs are guaranteed 12-bit monotonic over the full temperature range.
The AD7537 has a 2-byte (8 LSBs, 4 MSBs) loading structure. It is designed for right-justified data format. The control signals for register loading are A0, A1, CS, WR and UPD. Data is loaded to the input registers when CS and WR are low. To transfer this data to the DAC registers, UPD must be taken low with WR.
Added features on the AD7537 include an asynchronous CLR line which is very useful in calibration routines. When this is taken low, all registers are cleared. The double buffering of the data inputs allows simultaneous update of both DACs. Also, each DAC has a separate AGND line. This increases the device versatility; for instance one DAC may be operated with AGND biased while the other is connected in the standard configuration.
The AD7537 is manufactured using the Linear Compatible CMOS (LC2MOS) process. It is speed compatible with most microprocessors and accepts TTL, 74HC and 5 V CMOS logic level inputs.
AD7537 Data Sheet
