AD7492

AVDD to AGND/DGND . . . . . . . . . . . . . . . . . 0.3 V to +7 V
DV_DD to AGND/DGND . . . . . . . . . . . . . . . . . 0.3 V to +7 V
V_DRIVE to AGND/DGND . . . . . . . . . . . . . . . . 0.3 V to +7 V
AV_DD to DVDD . . . . . . . . . . . . . . . . . . . . .0.3 V to +0.3 V
V_DRIVE to DV_DD . . . . . . . . . . . . . . .0.3 V to DV_DD + 0.3 V
AGND TO DGND . . . . . . . . . . . . . . . . . . . .0.3 V to +0.3 V
Analog Input Voltage to AGND . . . 0.3 V to AV_DD + 0.3 V
Digital Input Voltage to DGND . . . 0.3 V to DV_DD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . ±10 mA
Operating Temperature Range
Commercial (A and B Versions) . . . . . 40°C to +85°C
Storage Temperature Range . . . . . .65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
SOIC, TSSOP Package Dissipation . . . . . . . . . . . . 450 mW
_JA Thermal Impedance . . . . . . . . . . . . .75°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . .115°C/W (TSSOP)
_JC Thermal Impedance . . . . . . . . . . . . .25°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35°C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2 Transient currents of up to 100 mA will not cause SCR latch-up.

The AD7492 and AD7492-5 are 12-bit high-speed, low power,successive-approximation ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1.25 MSPS. They contain a low-noise, wide bandwidth track/hold amplifier that can handle bandwidths up to 10 MHz.

The conversion process and data acquisition of AD7492 and AD7492-5 are controlled using standard control inputs allowing easy interface to microprocessors or DSPs. The input signal is sampled on the falling edge ofCONVST and conversion is also initiated at this point. The BUSY goes high at the start of conversion and goes low 880 ns (AD7492) or 680 ns (AD7492-5) later to indicate that the conversion is complete. There are no pipeline delays associated with the part. The conversion result is accessed via standard CS andRD signals over a high-speed parallel interface.

The AD7492 uses advanced design techniques to achieve very low power dissipation at high throughput rates. With 5 V supplies and 1.25 MSPS, the average current consumption AD7492-5 is typically 2.75 mA. The part also offers flexible power/throughput rate management.

AD7492 and AD7492-5 is also possible to operate the part in a full sleep mode and a partial sleep mode, where the part wakes up to do a conversion and automatically enters a sleep mode at the end of conversion.The type of sleep mode is hardware selected by the PS/FS pin.Using these sleep modes allows very low power dissipation numbers at lower throughput rates.

The analog input range for the part is 0 to REF IN. The 2.5 V reference is supplied internally and is available for external referencing.The conversion rate is determined by the internal clock of AD7492 and AD7492-5.