Features: Specified for VDD of 1.8 V to 3.6 VLow Power:0.9 mW max at 60 kSPS with 3.6 V Supplies0.4 mW max at 100 kSPS with 1.8 V SuppliesFast Throughput Rate: 100 kSPSWide Input Bandwidth:70dB SNR at 30 kHz Input FrequencyFlexible Power/Serial Clock Speed ManagementNo Pipeline DelaysHigh Speed Se...
AD7467: Features: Specified for VDD of 1.8 V to 3.6 VLow Power:0.9 mW max at 60 kSPS with 3.6 V Supplies0.4 mW max at 100 kSPS with 1.8 V SuppliesFast Throughput Rate: 100 kSPSWide Input Bandwidth:70dB SNR ...
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Resolution (Bits) | 10bit |
T-Put Rate | 200kSPS |
# Chan | 1 |
Supply V | Single(+1.8),Single(+2.5),Single(+3),Single(+3.3) |
Pwr Diss | 0.63mW |
Interface | Ser,SPI |
Ain Range | Uni Vdd |
SNR (dB) | 61dB |
Pkg Type | SOP,SOT |
The AD7466/AD7467/AD7468 are 12/10/8-bit, high speed, low power, successive-approximation ADCs respectively. The parts operate from a single 1.8 V to 3.6 V power supply and feature throughput rates up to 100 kSPS. The parts contain a low-noise, wide bandwidth track/hold amplifier which can handle input frequencies in excess of 100 kHz.
The conversion process and data acquisition of AD7466/AD7467/AD7468 are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipelined delays associated with the part.
The AD7466/AD7467/AD7468 use advanced design techniques to achieve very low power dissipation at high throughput rates.
The reference for the part is taken internally from VDD. This allows the widest dynamic input range to the ADC. Thus the analog input range for the part is 0 to VDD. The conversion rate is determined by the SCLK of AD7466/AD7467/AD7468.